mirror of https://github.com/openXC7/prjxray.git
72 lines
1.8 KiB
Tcl
72 lines
1.8 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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source ../../utils/utils.tcl
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# ----------------------------------------------------------
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set_property FIXED_ROUTE {} [get_nets o_OBUF]
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route_design -unroute
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route_via o_OBUF {
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INT_L_X12Y144/LVB_L12 INT_L_X12Y132/LVB_L12
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INT_L_X12Y120/SS6BEG2
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INT_L_X14Y120/NN6END3
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INT_L_X14Y132/LVB_L12 INT_L_X14Y144/LVB_L12
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INT_L_X16Y144/LVB_L12 INT_L_X16Y132/LVB_L12
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}
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# ----------------------------------------------------------
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route_design
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write_checkpoint -force design_a.dcp
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write_bitstream -force design_a.bit
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# ----------------------------------------------------------
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set_property FIXED_ROUTE {} [get_nets o_OBUF]
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route_design -unroute
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route_via o_OBUF {
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INT_L_X12Y120/NN6END3
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INT_L_X12Y132/LVB_L12 INT_L_X12Y144/LVB_L12
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INT_L_X14Y144/LVB_L12 INT_L_X14Y132/LVB_L12
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INT_L_X14Y120/SS6BEG2
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INT_L_X16Y120/NN6END3
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INT_L_X16Y132/LVB_L12 INT_L_X16Y144/LVB_L12
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INT_L_X16Y144/EE4BEG2
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}
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# ----------------------------------------------------------
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route_design
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write_checkpoint -force design_b.dcp
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write_bitstream -force design_b.bit
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