mirror of https://github.com/openXC7/prjxray.git
205 lines
3.5 KiB
Verilog
205 lines
3.5 KiB
Verilog
`include "src/iserdes_idelay_histogram.v"
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`include "src/idelay_calibrator.v"
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`include "src/error_counter.v"
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`include "src/message_formatter.v"
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`include "src/lfsr.v"
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`include "src/simpleuart.v"
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`default_nettype none
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// ============================================================================
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module top
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(
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input wire clk,
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input wire rx,
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output wire tx,
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input wire [15:0] sw,
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output wire [15:0] led,
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output wire ja1,
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output wire ja2,
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output wire ja3,
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output wire ja4,
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output wire ja7,
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output wire ja8,
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output wire ja9,
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output wire ja10,
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output wire jb1,
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output wire jb2,
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output wire jb3,
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output wire jb4,
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output wire jb7,
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output wire jb8,
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output wire jb9,
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output wire jb10,
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output wire jc1,
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output wire jc2,
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output wire jc3,
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output wire jc4,
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output wire jc7,
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output wire jc8,
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output wire jc9,
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output wire jc10,
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output wire xadc1_p,
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output wire xadc2_p,
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output wire xadc3_p,
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output wire xadc4_p,
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input wire xadc1_n,
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output wire xadc2_n,
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output wire xadc3_n,
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output wire xadc4_n
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);
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// ============================================================================
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// Clock & reset
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reg [3:0] rst_sr;
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initial rst_sr <= 4'hF;
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always @(posedge clk)
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if (sw[0])
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rst_sr <= 4'hF;
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else
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rst_sr <= rst_sr >> 1;
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wire pll_clkfb;
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wire pll_locked;
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wire CLK100;
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wire CLK200;
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wire CLK400;
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PLLE2_BASE #
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(
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.CLKFBOUT_MULT (8),
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.CLKOUT0_DIVIDE (8),
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.CLKOUT1_DIVIDE (4)
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)
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pll
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(
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.CLKIN1 (clk),
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.CLKFBIN (pll_clkfb),
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.CLKFBOUT (pll_clkfb),
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.CLKOUT0 (CLK100),
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.CLKOUT1 (CLK200),
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.RST (rst_sr[0]),
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.LOCKED (pll_locked)
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);
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// ============================================================================
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// IDELAY calibrator
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wire cal_rdy;
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idelay_calibrator cal
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(
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.refclk (CLK100),
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.rst (rst_sr[0] || !pll_locked),
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.rdy (cal_rdy)
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);
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wire RST = rst_sr[0] || !cal_rdy;
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// ============================================================================
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wire sig_out;
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wire sig_inp;
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wire [4:0] delay;
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wire sig_ref_i;
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wire sig_ref_o;
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wire sig_ref_c;
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iserdes_idelay_histogram #
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(
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.UART_PRESCALER (868)
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)
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iserdes_idelay_histogram
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(
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.CLK (CLK100),
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.RST (RST),
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.UART_RX (rx),
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.UART_TX (tx),
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.O (sig_out),
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.I (sig_inp),
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.REF_O (sig_ref_o),
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.REF_I (sig_ref_i),
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.REF_C (sig_ref_c),
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.DELAY (delay)
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);
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// ============================================================================
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// I/O connections
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reg [23:0] heartbeat_cnt;
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always @(posedge CLK100)
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heartbeat_cnt <= heartbeat_cnt + 1;
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assign led[ 0] = heartbeat_cnt[23];
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assign led[ 1] = cal_rdy;
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assign led[ 2] = 1'b0;
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assign led[ 3] = 1'b0;
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assign led[ 4] = 1'b0;
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assign led[ 5] = 1'b0;
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assign led[ 6] = 1'b0;
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assign led[ 7] = 1'b0;
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assign led[ 8] = 1'b0;
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assign led[ 9] = 1'b0;
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assign led[10] = 1'b0;
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assign led[11] = delay[0];
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assign led[12] = delay[1];
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assign led[13] = delay[2];
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assign led[14] = delay[3];
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assign led[15] = delay[4];
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assign ja1 = 1'b0;
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assign ja2 = 1'b0;
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assign ja3 = 1'b0;
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assign ja4 = 1'b0;
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assign ja7 = 1'b0;
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assign ja8 = 1'b0;
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assign ja9 = 1'b0;
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assign ja10 = 1'b0;
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assign jb1 = 1'b0;
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assign jb2 = 1'b0;
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assign jb3 = 1'b0;
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assign jb4 = 1'b0;
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assign jb7 = 1'b0;
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assign jb8 = 1'b0;
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assign jb9 = 1'b0;
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assign jb10 = 1'b0;
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assign jc1 = 1'b0;
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assign jc2 = 1'b0;
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assign jc3 = 1'b0;
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assign jc4 = 1'b0;
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assign jc7 = 1'b0;
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assign jc8 = 1'b0;
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assign jc9 = 1'b0;
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assign jc10 = 1'b0;
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assign xadc1_p = sig_ref_i;
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assign xadc2_p = sig_ref_o;
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assign xadc3_p = sig_ref_c;
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assign xadc4_p = 1'b0;
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//assign xadc1_n = 1'b0;
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assign xadc2_n = sig_out;
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assign xadc3_n = 1'b0;
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assign xadc4_n = 1'b0;
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assign sig_inp = xadc1_n;
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endmodule
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