prjxray/minitests/fixedpnr/top_ldpe.v

14 lines
195 B
Verilog

module top(input clk, ce, sr, d, output q);
(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
//Keep inverter off
LDPE_1 ff (
.G(clk),
.GE(ce),
.PRE(sr),
.D(d),
.Q(q)
);
endmodule