mirror of https://github.com/openXC7/prjxray.git
57 lines
2.2 KiB
Tcl
57 lines
2.2 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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source ../../utils/utils.tcl
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proc get_rand_lut6_init {} {
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return "64'h[format %08x [expr int(rand() * 65536 * 65536)]][format %08x [expr int(rand() * 65536 * 65536)]]"
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}
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set i 1
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foreach site [randsample_list 100 [get_sites -of_objects [get_pblocks roi]]] {
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puts "$i/100: $site"
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incr i
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create_cell -reference LUT6 LUT_${site}_ALUT
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create_cell -reference LUT6 LUT_${site}_BLUT
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create_cell -reference LUT6 LUT_${site}_CLUT
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create_cell -reference LUT6 LUT_${site}_DLUT
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set_property -dict "LOC $site BEL A6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_ALUT]
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set_property -dict "LOC $site BEL B6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_BLUT]
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set_property -dict "LOC $site BEL C6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_CLUT]
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set_property -dict "LOC $site BEL D6LUT INIT [get_rand_lut6_init]" [get_cells LUT_${site}_DLUT]
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connect_net -net [get_nets y_OBUF] -objects [get_pins "
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LUT_${site}_ALUT/I0 LUT_${site}_ALUT/I1 LUT_${site}_ALUT/I2 LUT_${site}_ALUT/I3 LUT_${site}_ALUT/I4 LUT_${site}_ALUT/I5
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LUT_${site}_BLUT/I0 LUT_${site}_BLUT/I1 LUT_${site}_BLUT/I2 LUT_${site}_BLUT/I3 LUT_${site}_BLUT/I4 LUT_${site}_BLUT/I5
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LUT_${site}_CLUT/I0 LUT_${site}_CLUT/I1 LUT_${site}_CLUT/I2 LUT_${site}_CLUT/I3 LUT_${site}_CLUT/I4 LUT_${site}_CLUT/I5
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LUT_${site}_DLUT/I0 LUT_${site}_DLUT/I1 LUT_${site}_DLUT/I2 LUT_${site}_DLUT/I3 LUT_${site}_DLUT/I4 LUT_${site}_DLUT/I5
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"]
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}
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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