mirror of https://github.com/openXC7/prjxray.git
24 lines
589 B
Verilog
24 lines
589 B
Verilog
module top (input ci, input cyinit, input s0, output o0);
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wire [3:0] o, passthru_co, passthru_o;
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CARRY4 carry4_inst (
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// This will produce the following warning, but will still generate a bitstream.. needs some testing in hardware.
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// WARNING: [DRC REQP-16] virt5_carry4_input_rule1: CYINIT and CI of carry4_inst cannot be used at the same time.
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.CI(passthru_co[3]),
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.CYINIT(cyinit),
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.DI(4'b0000),
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.S({3'b000, s0}),
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.O(o)
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);
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CARRY4 carry4_passthru (
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.CI(1'b1),
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.CYINIT(1'b1),
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.DI({ci, 3'b000}),
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.S(4'b0000),
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.CO(passthru_co)
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);
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assign o0 = o[0];
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endmodule
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