mirror of https://github.com/openXC7/prjxray.git
87 lines
1.6 KiB
Verilog
87 lines
1.6 KiB
Verilog
//move some stuff to minitests/ncy0
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 256;
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localparam integer DOUT_N = 256;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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clb_FF clb_FF (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8]));
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clb_OUT clb_OUT (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8]));
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endmodule
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module clb_FF (input clk, input [7:0] din, output [7:0] dout);
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wire o6;
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//assign dout[0] = o6;
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(* LOC="SLICE_X18Y100", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(o6));
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(* LOC="SLICE_X18Y100", BEL="BFF" *)
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FDPE ff (
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.C(clk),
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.Q(dout[1]),
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.CE(din[0]),
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.PRE(din[1]),
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.D(o6));
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endmodule
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module clb_OUT (input clk, input [7:0] din, output [7:0] dout);
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wire o6;
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assign dout[0] = o6;
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(* LOC="SLICE_X18Y101", BEL="B6LUT", KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(o6));
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(* LOC="SLICE_X18Y101", BEL="BFF" *)
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FDPE ff (
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.C(clk),
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.Q(dout[1]),
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.CE(din[0]),
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.PRE(din[1]),
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.D(o6));
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endmodule
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