mirror of https://github.com/openXC7/prjxray.git
127 lines
2.6 KiB
Verilog
127 lines
2.6 KiB
Verilog
module top (
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);
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// Both RAMB18 in the same tile
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y25" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_BOTH_X1 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y24" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_BOTH_X0 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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// ---------------------------------------
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// One RAMB18 in Y0
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y22" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_X0 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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// ---------------------------------------
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// One RAMB18 in Y1
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(* KEEP, DONT_TOUCH, LOC="RAMB18_X0Y21" *)
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RAMB18E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(36),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(36)
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) RAMB18E1_X1 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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// ---------------------------------------
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// One RAMB36
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(* KEEP, DONT_TOUCH, LOC="RAMB36_X0Y9" *)
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RAMB36E1 #(
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.RAM_MODE("SDP"),
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.READ_WIDTH_A(72),
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.READ_WIDTH_B(0),
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.WRITE_MODE_A("READ_FIRST"),
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.WRITE_MODE_B("READ_FIRST"),
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.WRITE_WIDTH_A(0),
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.WRITE_WIDTH_B(72)
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) RAMB36E1_X0 (
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.ENARDEN(1'b1),
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.ENBWREN(1'b1),
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.REGCEAREGCE(1'b1),
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.REGCEB(1'b0),
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.RSTRAMARSTRAM(1'b1),
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.RSTRAMB(1'b1),
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.RSTREGARSTREG(1'b1),
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.RSTREGB(1'b1),
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.WEA({1'b0}),
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.WEBWE({1'b0})
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);
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endmodule
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