mirror of https://github.com/openXC7/prjxray.git
181 lines
6.1 KiB
Python
181 lines
6.1 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker, add_site_group_zero
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from prjxray.verilog import to_int
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from prjxray.verilog import quote
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import json
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def add(segmk, site, dsp, tag, bit, value, invert, is_vector=True):
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tag = "%s.%s%s%s" % (
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dsp, ('Z' if invert else ''), tag, '[%u]' % bit if is_vector else '')
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value = (~value if invert else value)
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value >>= bit
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return segmk.add_site_tag(site, tag, value & 1)
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def run():
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segmk = Segmaker("design.bits", verbose=True)
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print("Loading tags")
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with open('params.json', 'r') as fp:
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data = json.load(fp)
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used_dsps = set()
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for params in data['instances']:
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dsp = "DSP_0" if params['SITE'][-1] in "02468" else "DSP_1"
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site = params['SITE']
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if params['USE_DPORT'] == quote(
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"TRUE") and params['USE_MULT'] != quote("NONE"):
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add(segmk, site, dsp, 'ADREG', 0, to_int(params['ADREG']), 1)
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add(segmk, site, dsp, 'ALUMODEREG', 0, to_int(params['ALUMODEREG']), 1)
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if params['A_INPUT'] == quote("DIRECT"):
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add(
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segmk, site, dsp, 'AREG_0', 0,
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int(to_int(params['AREG']) == 0), 0, False)
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add(
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segmk, site, dsp, 'AREG_2', 0,
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int(to_int(params['AREG']) == 2), 0, False)
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if params['B_INPUT'] == quote("DIRECT"):
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add(
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segmk, site, dsp, 'BREG_0', 0,
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int(to_int(params['BREG']) == 0), 0, False)
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add(
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segmk, site, dsp, 'BREG_2', 0,
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int(to_int(params['BREG']) == 2), 0, False)
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if params['A_INPUT'] == quote("CASCADE"):
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add(
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segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
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int(
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to_int(params['AREG']) == 2
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and to_int(params['ACASCREG']) == 1), 0, False)
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add(
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segmk, site, dsp, 'AREG_2_ACASCREG_1', 0,
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int(
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to_int(params['AREG']) == 2
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and to_int(params['ACASCREG']) == 1), 1, False)
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if params['B_INPUT'] == quote("CASCADE"):
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add(
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segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
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int(
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to_int(params['BREG']) == 2
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and to_int(params['BCASCREG']) == 1), 0, False)
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add(
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segmk, site, dsp, 'BREG_2_BCASCREG_1', 0,
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int(
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to_int(params['BREG']) == 2
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and to_int(params['BCASCREG']) == 1), 1, False)
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add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1)
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add(
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segmk, site, dsp, 'CARRYINSELREG', 0,
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to_int(params['CARRYINSELREG']), 1)
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add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1)
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if params['USE_DPORT'] == quote(
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"TRUE") and params['USE_MULT'] != quote("NONE"):
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add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 1)
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add(segmk, site, dsp, 'INMODEREG', 0, to_int(params['INMODEREG']), 1)
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add(segmk, site, dsp, 'OPMODEREG', 0, to_int(params['OPMODEREG']), 1)
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add(segmk, site, dsp, 'PREG', 0, to_int(params['PREG']), 1)
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INPUT = {}
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INPUT[quote('DIRECT')] = 0
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INPUT[quote('CASCADE')] = 1
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add(segmk, site, dsp, 'A_INPUT', 0, INPUT[params['A_INPUT']], 0)
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add(segmk, site, dsp, 'B_INPUT', 0, INPUT[params['B_INPUT']], 0)
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BOOL = {}
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BOOL[quote('FALSE')] = 0
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BOOL[quote('TRUE')] = 1
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add(segmk, site, dsp, 'USE_DPORT', 0, BOOL[params['USE_DPORT']], 0)
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add(
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segmk, site, dsp, 'USE_SIMD_FOUR12', 0,
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params['USE_SIMD'] == quote("FOUR12"), 0, False)
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add(
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segmk, site, dsp, 'USE_SIMD_FOUR12_TWO24', 0,
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params['USE_SIMD'] in (quote("TWO24"), quote("FOUR12")), 0, False)
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MULT = {}
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MULT[quote('NONE')] = 0
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MULT[quote('MULTIPLY')] = 1
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MULT[quote('DYNAMIC')] = 2
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for i in range(2):
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add(segmk, site, dsp, 'USE_MULT', i, MULT[params['USE_MULT']], 0)
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add(segmk, site, dsp, 'MREG', 0, to_int(params['MREG']), 1)
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AUTORESET = {}
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AUTORESET[quote('NO_RESET')] = 0
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AUTORESET[quote('RESET_NOT_MATCH')] = 1
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AUTORESET[quote('RESET_MATCH')] = 2
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add(
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segmk, site, dsp, 'AUTORESET_PATDET_RESET_NOT_MATCH', 0,
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params['AUTORESET_PATDET'] == quote("RESET_NOT_MATCH"), 0, False)
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add(
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segmk, site, dsp, 'AUTORESET_PATDET_RESET', 0,
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params['AUTORESET_PATDET'] in (
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quote("RESET_NOT_MATCH"), quote("RESET_MATCH")), 0, False)
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for i in range(48):
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add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0)
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for i in range(48):
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add(segmk, site, dsp, 'PATTERN', i, to_int(params['PATTERN']), 0)
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if params['USE_PATTERN_DETECT'] == quote("PATDET"):
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add_site_group_zero(
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segmk, site, dsp + ".", [
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"SEL_MASK_%s" % x
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for x in ["MASK", "C", "ROUNDING_MODE1", "ROUNDING_MODE2"]
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], "SEL_MASK_MASK", "SEL_MASK_%s" % (params['SEL_MASK'][1:-1]))
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USE_PATTERN_DETECT = {}
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USE_PATTERN_DETECT[quote('NO_PATDET')] = 0
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USE_PATTERN_DETECT[quote('PATDET')] = 1
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add(
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segmk, site, dsp, 'USE_PATTERN_DETECT', 0,
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USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0)
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inv_ports = [
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("ALUMODE", 4),
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("CARRYIN", 1),
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("CLK", 1),
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("INMODE", 5),
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("OPMODE", 7),
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]
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for port, width in inv_ports:
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param = 'IS_{}_INVERTED'.format(port)
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for i in range(width):
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add(
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segmk, site, dsp, param, i, to_int(params[param]), 1,
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width > 1)
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segmk.compile()
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segmk.write()
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if __name__ == '__main__':
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run()
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