mirror of https://github.com/openXC7/prjxray.git
259 lines
7.3 KiB
Python
259 lines
7.3 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import json
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import os
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import random
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from collections import namedtuple
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import verilog
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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INT = "INT"
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BIN = "BIN"
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def gen_sites(tile, site, filter_cmt=None):
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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if tile not in gridinfo.tile_type:
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continue
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else:
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tile_type = gridinfo.tile_type
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for site_name, site_type in gridinfo.sites.items():
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if site_type != site:
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continue
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cmt = gridinfo.clock_region
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if filter_cmt is not None and cmt != filter_cmt:
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continue
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yield tile_name, tile_type, site_name, cmt
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def main():
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print(
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'''
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module top(
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input wire in,
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output wire out
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);
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assign out = in;
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''')
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luts = LutMaker()
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params_dict = {"tile_type": None}
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params_list = list()
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clkswing_cfg_tiles = dict()
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ibufds_out_wires = dict()
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for tile_name, _, site_name, _ in gen_sites("GTP_COMMON", "IBUFDS_GTE2"):
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# Both the IBUFDS_GTE2 in the same tile need to have
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# the same CLKSWING_CFG parameter
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if tile_name not in clkswing_cfg_tiles:
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clkswing_cfg = random.randint(0, 3)
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clkswing_cfg_tiles[tile_name] = clkswing_cfg
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else:
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clkswing_cfg = clkswing_cfg_tiles[tile_name]
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in_use = bool(random.randint(0, 9))
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params = {
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"site":
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site_name,
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"tile":
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tile_name,
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"IN_USE":
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in_use,
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"CLKRCV_TRST":
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verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
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"CLKCM_CFG":
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verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
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"CLKSWING_CFG":
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clkswing_cfg,
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}
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if in_use:
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ibufds_out_wire = "{}_O".format(site_name)
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if tile_name not in ibufds_out_wires:
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ibufds_out_wires[tile_name] = list()
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ibufds_out_wires[tile_name].append(
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(ibufds_out_wire, int(site_name[-1]) % 2))
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print("wire {};".format(ibufds_out_wire))
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print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
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print(
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"""
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IBUFDS_GTE2 #(
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.CLKRCV_TRST({CLKRCV_TRST}),
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.CLKCM_CFG({CLKCM_CFG}),
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.CLKSWING_CFG({CLKSWING_CFG})
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) {site} (
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.O({out})
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);""".format(**params, out=ibufds_out_wire))
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params_list.append(params)
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DRP_PORTS = [
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("DRPCLK", "clk"), ("DRPEN", "in"), ("DRPWE", "in"), ("DRPRDY", "out")
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]
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for tile_name, tile_type, site_name, cmt in gen_sites("GTP_COMMON",
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"GTPE2_COMMON"):
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params_dict["tile_type"] = tile_type
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params = dict()
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params['site'] = site_name
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params['tile'] = tile_name
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verilog_attr = ""
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verilog_attr = "#("
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fuz_dir = os.getenv("FUZDIR", None)
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assert fuz_dir
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with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
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attrs = json.load(attrs_file)
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in_use = bool(random.randint(0, 9))
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params["IN_USE"] = in_use
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if in_use:
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for param, param_info in attrs.items():
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param_type = param_info["type"]
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param_values = param_info["values"]
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param_digits = param_info["digits"]
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if param_type == INT:
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value = random.choice(param_values)
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value_str = value
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else:
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assert param_type == BIN
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value = random.randint(0, param_values[0])
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value_str = "{digits}'b{value:0{digits}b}".format(
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value=value, digits=param_digits)
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params[param] = value
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verilog_attr += """
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.{}({}),""".format(param, value_str)
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verilog_ports = ""
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for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
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is_inverted = random.randint(0, 1)
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params[param] = is_inverted
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verilog_attr += """
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.IS_{}_INVERTED({}),""".format(param, is_inverted)
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verilog_ports += """
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.{}({}),""".format(param, luts.get_next_output_net())
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verilog_attr = verilog_attr.rstrip(",")
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verilog_attr += "\n)"
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for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
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"BOTH_GTREFCLK_USED"]:
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params[param] = 0
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if tile_name in ibufds_out_wires:
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gtrefclk_ports_used = 0
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for wire, location in ibufds_out_wires[tile_name]:
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if random.random() < 0.5:
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continue
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verilog_ports += """
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.GTREFCLK{}({}),""".format(location, wire)
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gtrefclk_ports_used += 1
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params["GTREFCLK{}_USED".format(location)] = 1
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if gtrefclk_ports_used == 2:
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params["BOTH_GTREFCLK_USED"] = 1
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enable_drp = random.randint(0, 1)
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params["ENABLE_DRP"] = enable_drp
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for _, _, channel_site_name, _ in gen_sites("GTP_CHANNEL",
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"GTPE2_CHANNEL", cmt):
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if not enable_drp:
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break
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verilog_ports_channel = ""
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for port, direction in DRP_PORTS:
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if direction == "in":
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verilog_ports_channel += """
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.{}({}),""".format(port, luts.get_next_output_net())
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elif direction == "clk":
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# DRPCLK needs to come from a clock source
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print(
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"""
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wire clk_bufg_{site};
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(* KEEP, DONT_TOUCH *)
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BUFG bufg_{site} (.O(clk_bufg_{site}));""".format(site=channel_site_name))
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verilog_ports_channel += """
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.{}(clk_bufg_{}),""".format(port, channel_site_name)
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elif direction == "out":
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verilog_ports_channel += """
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.{}({}),""".format(port, luts.get_next_input_net())
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC=\"{site}\" *)
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GTPE2_CHANNEL {site} (
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{ports}
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);""".format(ports=verilog_ports_channel.rstrip(","), site=channel_site_name))
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC=\"{site}\" *)
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GTPE2_COMMON {attrs} {site} (
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{ports}
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);""".format(
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attrs=verilog_attr,
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ports=verilog_ports.rstrip(","),
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site=site_name))
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params_list.append(params)
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for l in luts.create_wires_and_luts():
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print(l)
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print("endmodule")
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params_dict["params"] = params_list
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with open('params.json', 'w') as f:
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json.dump(params_dict, f, indent=2)
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if __name__ == '__main__':
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main()
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