mirror of https://github.com/openXC7/prjxray.git
141 lines
4.6 KiB
Tcl
141 lines
4.6 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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# This fuzzer occasionally fails on the PDIL-1 DRC
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# PDIL-1 stands for Invalid site configuration which according to UG912
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# happens when the route connects to a site pin on a site where the
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# programming of the site is in an invalid state.
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# Since in case of this fuzzer the routing path is random due to
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# non-deterministic choice of source and destination pins
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# we can lower the severity of the PDIL-1 DRC in order to
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# prevent the termination of the execution of the script.
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proc disable_drc_errors {} {
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set_property SEVERITY {Warning} [get_drc_checks PDIL-1]
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}
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proc build_basic {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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}
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proc load_todo {} {
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set fp [open "../../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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}
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close $fp
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return $todo_lines
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}
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proc lremove { l val } {
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set idx [lsearch $l $val]
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return [lreplace $l $idx $idx]
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}
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proc route_todo {} {
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set todo_lines [load_todo]
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set int_l_tiles [filter [pblock_tiles roi] {TYPE == INT_L}]
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set int_r_tiles [filter [pblock_tiles roi] {TYPE == INT_R}]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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puts ""
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puts ""
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puts "== $idx: $line"
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set mynet [create_net mynet_$idx]
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connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
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set tries 0
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while {1} {
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incr tries
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puts ""
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puts "$mynet: try $tries"
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if {$tile_type == "INT_L"} {
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set tile [randsample_list 1 $int_l_tiles]
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set int_l_tiles [lremove $int_l_tiles $tile]
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set other_tile [randsample_list 1 $int_r_tiles]
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set int_r_tiles [lremove $int_r_tiles $other_tile]
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} elseif {$tile_type == "INT_R"} {
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set tile [randsample_list 1 $int_r_tiles]
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set int_r_tiles [lremove $int_r_tiles $tile]
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set other_tile [randsample_list 1 $int_l_tiles]
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set int_l_tiles [lremove $int_l_tiles $other_tile]
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} else {
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error "Bad tile type $tile_type"
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}
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puts "PIP Tile: $tile, LUT tile: $other_tile"
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set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
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-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
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puts "LUT site: $driver_site"
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set_property -dict "LOC $driver_site BEL A6LUT" $mylut
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set route_list "$tile/$src_wire $tile/$dst_wire"
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puts "route_via $mynet $route_list"
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set rc [route_via $mynet $route_list 0]
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if {$rc != 0} {
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break
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}
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puts "WARNING: failed to route net"
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write_checkpoint -force route_todo_$idx.$tries.fail.dcp
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puts "Rolling back route"
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set_property is_route_fixed 0 $mynet
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set_property is_bel_fixed 0 $mylut
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set_property is_loc_fixed 1 $mylut
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route_design -unroute -nets $mynet
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# sometimes it gets stuck in specific orientations
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if {$tries >= 3} {
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puts "WARNING: failed to route net after $tries tries"
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remove_net $mynet
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remove_cell $mylut
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break
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}
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}
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}
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}
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proc run {} {
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build_basic
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disable_drc_errors
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route_todo
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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