mirror of https://github.com/openXC7/prjxray.git
164 lines
6.5 KiB
Tcl
164 lines
6.5 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog $::env(FUZDIR)/top.v
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read_verilog $::env(FUZDIR)/picorv32.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports din]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports dout]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set_param tcl.collectionResultDisplayLimit 0
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place_design
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route_design
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# write_checkpoint -force design.dcp
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proc find_dst_pin {tile dst_wire} {
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# This function finds a CLB pin in a $tile which can be driven by the $dst_wire.
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# The pin may not be directly driven by the wire, so the function follows possible
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# routing path until it finds the desired pin.
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puts "Looking for dst pin for wire $tile/$dst_wire"
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set next_dst_wire $dst_wire
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set iterations 0
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while {$iterations < 10} {
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set iterations [expr $iterations + 1]
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set clb_dst_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$next_dst_wire]]]
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# the selected wire does not connect to any CLB wire let's go further and try to find a CLB pin
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if {$clb_dst_wire == ""} {
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# BOUNCE* pips may lead to a different CLB
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set pips [get_pips -regexp -downhill -of_objects [get_wire $tile/$next_dst_wire] (?!.*BOUNCE).*]
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# choose a random pip and check if it will lead us to a CLB
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set next_pip [lindex $pips [expr {int(rand()*[llength $pips])}]]
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set next_dst_wire [regsub {.*->>(.*)} $next_pip {\1}]
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} else {
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set clb_dst_pin [get_site_pins -of_objects [get_nodes -downhill -of_objects [get_pips -of_objects $clb_dst_wire]]]
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return $clb_dst_pin
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}
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}
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error "ERROR: Unable to find destination pin for wire $tile/$dst_wire (iterations: $iterations)"
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}
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proc find_src_pin {tile src_wire} {
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# This function finds a CLB pin in a $tile which can drive the $src_wire
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# The wire may not be directly driven by the pin, so the function follows
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# possible routing path until it finds the desired pin.
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puts "Looking for src pin for wire $tile/$src_wire"
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set next_src_wire $src_wire
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set iterations 0
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while {$iterations < 10} {
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set iterations [expr $iterations + 1]
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set clb_src_wire [get_wires -filter {TILE_NAME =~ CLB*} -of_objects [get_nodes -of_objects [get_wire $tile/$next_src_wire]]]
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# the selected wire does not connect to any CLB wire let's go further and try to find a CLB pin
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if {$clb_src_wire == ""} {
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set pips [get_pips -uphill -of_objects [get_wire $tile/$next_src_wire]]
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# choose a random pip and check if it will lead us to a CLB
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set next_pip [lindex $pips [expr {int(rand()*[llength $pips])}]]
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set next_src_wire [regsub {(.*)->>.*} $next_pip {\1}]
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} else {
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set clb_src_pin [get_site_pins -of_objects [get_nodes -uphill -of_objects [get_pips -of_objects $clb_src_wire]]]
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return $clb_src_pin
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}
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}
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error "ERROR: Unable to find source pin for $tile/$src_wire (iterations: $iterations)"
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}
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set fp [open "../../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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}
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close $fp
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set int_l_tiles [filter [pblock_tiles roi] {TYPE == INT_L}]]
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set int_r_tiles [filter [pblock_tiles roi] {TYPE == INT_R}]]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]}
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if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]}
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set clb_dst_pin [find_dst_pin $tile $dst_wire]
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set clb_src_pin [find_src_pin $tile $src_wire]
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set src_prefix [regsub {(.*/.).*} ${clb_src_pin} {\1}]
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set dst_prefix [regsub {(.*/.).*} ${clb_dst_pin} {\1}]
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set slice [get_sites -of_objects $clb_dst_pin]
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set src_slice [get_sites -of_objects $clb_src_pin]
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set lut [regsub {.*/} $src_prefix {}]6LUT
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set dff [regsub {.*/} $src_prefix {}]FF
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set mynet [create_net mynet_$idx]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set dst_type [regsub {.*(.$)} $clb_dst_pin {\1}]
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set lutin [regsub {.*(.)} $clb_dst_pin {A\1}]
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# some dst pins are not LUT inputs so they do not have LOCK_PINS property
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if { $dst_type >= 0 && $dst_type <= 6 } {
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set_property -dict "LOC $slice BEL $lut LOCK_PINS I0:$lutin" $mylut
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} else {
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set_property -dict "LOC $slice BEL $lut" $mylut
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}
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# some source wires may be FF outputs, in such cases
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# we need to place and route an FF
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set src_type [regsub {.*/*(.$)} $clb_src_pin {\1}]
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if { $src_type == "Q" } {
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set mydff [create_cell -reference FDCE mydff_$idx]
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set_property -dict "LOC $src_slice BEL $dff" $mydff
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connect_net -net $mynet -objects "$mylut/I0 $mydff/Q"
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} else {
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connect_net -net $mynet -objects "$mylut/I0 $mylut/O"
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}
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set route_list "$tile/$src_wire $tile/$dst_wire"
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puts "route_via $mynet $route_list"
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set rc [route_via $mynet $route_list 0]
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if {$rc != 0} {
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puts "SUCCESS"
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} else {
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puts "Manual routing failed"
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# TODO: We should probably fail here
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}
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}
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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# quick: only analyze manually routed tiles, skipping riscv and such
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if {[info exists ::env(QUICK) ] && "$::env(QUICK)" == "Y"} {
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set lim [expr [llength $todo_lines] - 1]
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set tiles [concat [lrange $int_l_tiles 0 $lim] [lrange $int_r_tiles 0 $lim]]
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} else {
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set tiles [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]]
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}
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write_pip_txtdata design.txt
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