mirror of https://github.com/openXC7/prjxray.git
480 lines
15 KiB
Python
480 lines
15 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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""" Emits top.v's for various BUFHCE routing inputs. """
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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from io import StringIO
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CMT_XY_FUN = util.create_xy_fun(prefix='')
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def read_site_to_cmt():
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""" Yields clock sources and which CMT they route within. """
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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class ClockSources(object):
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""" Class for tracking clock sources.
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"""
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def __init__(self, limit=14):
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self.sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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self.limit = limit
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def add_clock_source(self, source, cmt):
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""" Adds a source from a specific CMT.
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cmt='ANY' indicates that this source can be routed to any CMT.
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"""
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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self.source_to_cmt[source] = cmt
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def get_random_source(self, cmt, no_repeats=False):
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""" Get a random source that is routable to the specific CMT.
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get_random_source will return a source that is either cmt='ANY',
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cmt equal to the input CMT, or the adjecent CMT.
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"""
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choices = []
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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random.shuffle(choices)
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for source in choices:
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source_cmt = self.source_to_cmt[source]
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if source_cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[source_cmt] = set()
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if no_repeats and source in self.used_sources_from_cmt[source_cmt]:
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continue
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if len(self.used_sources_from_cmt[source_cmt]) >= self.limit:
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continue
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self.used_sources_from_cmt[source_cmt].add(source)
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return source
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return None
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def main():
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"""
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HCLK_IOI has the following inputs:
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12 (east) BUFH from the right side of the HROW
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12 (west) Bounce PIPs from one BUFH to any of 6 GCLK_BOT and 6 GCLK_TOP
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4 (east) PHSR_PERFCLK (IOCLK_PLL) from HCLK_CLB to input of BUFIO
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8 (4 north and 4 south) BUFR CLR and CE
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2 (south) I2IOCLK to input of BUFR
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2 (north) I2IOCLK to input of BUFR
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2 RCLK IMUX (IMUX0 and IMUX1) choosing input of BUFR
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outputs:
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4 (east) BUFRCLK - from BUFR to HROW
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4 (north) BUFR2IO - from BUFR
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4 (north) IOCLK from BUFIO
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"""
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global_clock_sources = ClockSources()
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cmt_clock_sources = ClockSources()
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cmt_fast_clock_sources = ClockSources(4)
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bufr_clock_sources = ClockSources()
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bufio_clock_sources = ClockSources()
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site_to_cmt = dict(read_site_to_cmt())
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clock_region_limit = dict()
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clock_region_serdes_location = dict()
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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def gen_sites(desired_site_type):
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield tile_name, site
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def serdes_relative_location(tile, site):
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(serdes_loc_x, serdes_loc_y) = grid.loc_of_tilename(tile)
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serdes_clk_reg = site_to_cmt[site]
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for tile_name in sorted(grid.tiles()):
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if 'HCLK_IOI3' in tile_name:
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(hclk_tile_loc_x,
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hclk_tile_loc_y) = grid.loc_of_tilename(tile_name)
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if hclk_tile_loc_x == serdes_loc_x:
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gridinfo = grid.gridinfo_at_loc(
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(hclk_tile_loc_x, hclk_tile_loc_y))
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random_site = next(iter(gridinfo.sites.keys()))
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hclk_clk_reg = site_to_cmt[random_site]
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if hclk_clk_reg == serdes_clk_reg:
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if serdes_loc_y < hclk_tile_loc_y:
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return "TOP"
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elif serdes_loc_y > hclk_tile_loc_y:
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return "BOTTOM"
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else:
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assert False
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clock_region_sites = set()
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def get_clock_region_site(site_type, clk_reg):
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for site_name, reg in site_to_cmt.items():
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if site_name.startswith(site_type) and reg in clk_reg:
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if site_name not in clock_region_sites:
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clock_region_sites.add(site_name)
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return site_name
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print(
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'''
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module top();
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy();
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''')
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luts = LutMaker()
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bufs = StringIO()
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for _, site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = [
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'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(13)
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]
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for idx, clk in enumerate(mmcm_clocks):
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if idx < 4:
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cmt_fast_clock_sources.add_clock_source(clk, site_to_cmt[site])
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else:
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cmt_clock_sources.add_clock_source(clk, site_to_cmt[site])
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print(
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"""
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wire cin1_{site}, cin2_{site}, clkfbin_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV pll_{site} (
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.CLKIN1(cin1_{site}),
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.CLKIN2(cin2_{site}),
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.CLKFBIN(clkfbin_{site}),
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.CLKOUT0({c0}),
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.CLKOUT0B({c4}),
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.CLKOUT1({c1}),
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.CLKOUT1B({c5}),
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.CLKOUT2({c2}),
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.CLKOUT2B({c6}),
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.CLKOUT3({c3}),
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.CLKOUT3B({c7}),
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.CLKOUT4({c8}),
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.CLKOUT5({c9}),
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.CLKOUT6({c10}),
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.CLKFBOUT({c11}),
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.CLKFBOUTB({c12})
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);
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""".format(
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2],
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c3=mmcm_clocks[3],
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c4=mmcm_clocks[4],
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c5=mmcm_clocks[5],
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c6=mmcm_clocks[6],
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c7=mmcm_clocks[7],
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c8=mmcm_clocks[8],
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c9=mmcm_clocks[9],
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c10=mmcm_clocks[10],
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c11=mmcm_clocks[11],
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c12=mmcm_clocks[12],
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))
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for _, site in gen_sites('PLLE2_ADV'):
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pll_clocks = [
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'pll_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(7)
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]
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for clk in pll_clocks:
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cmt_clock_sources.add_clock_source(clk, site_to_cmt[site])
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print(
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"""
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wire cin1_{site}, cin2_{site}, clkfbin_{site}, {c0}, {c1}, {c2}, {c3}, {c4}, {c5}, {c6};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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PLLE2_ADV pll_{site} (
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.CLKIN1(cin1_{site}),
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.CLKIN2(cin2_{site}),
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.CLKFBIN(clkfbin_{site}),
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.CLKOUT0({c0}),
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.CLKOUT1({c1}),
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.CLKOUT2({c2}),
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.CLKOUT3({c3}),
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.CLKOUT4({c4}),
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.CLKOUT5({c5}),
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.CLKFBOUT({c6})
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);
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""".format(
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site=site,
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c0=pll_clocks[0],
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c1=pll_clocks[1],
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c2=pll_clocks[2],
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c3=pll_clocks[3],
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c4=pll_clocks[4],
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c5=pll_clocks[5],
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c6=pll_clocks[6],
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))
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for tile_name, site in gen_sites('BUFHCE'):
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print(
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"""
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wire I_{site};
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wire O_{site};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFHCE buf_{site} (
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.I(I_{site}),
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.O(O_{site})
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);""".format(site=site),
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file=bufs)
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global_clock_sources.add_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site])
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hclks_used_by_clock_region = {}
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for cmt in site_to_cmt.values():
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hclks_used_by_clock_region[cmt] = set()
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def check_hclk_src(src, src_cmt):
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if len(hclks_used_by_clock_region[src_cmt]
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) >= 12 and src not in hclks_used_by_clock_region[src_cmt]:
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return None
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else:
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hclks_used_by_clock_region[src_cmt].add(src)
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return src
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cmt_clks_used_by_clock_region = {}
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for cmt in site_to_cmt.values():
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cmt_clks_used_by_clock_region[cmt] = list()
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def check_cmt_clk_src(src, src_clock_region):
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print(
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"//src: {}, clk_reg: {}, len {}".format(
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src, src_clock_region,
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len(cmt_clks_used_by_clock_region[src_clock_region])))
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if len(cmt_clks_used_by_clock_region[src_clock_region]) >= 4:
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return None
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else:
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cmt_clks_used_by_clock_region[src_clock_region].append(src)
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return src
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#Add IDELAYCTRL
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idelayctrl_in_clock_region = {}
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for cmt in site_to_cmt.values():
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idelayctrl_in_clock_region[cmt] = False
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for _, site in gen_sites('IDELAYCTRL'):
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if random.random() < 0.5:
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wire_name = global_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=False)
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if wire_name is None:
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continue
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src_cmt = global_clock_sources.source_to_cmt[wire_name]
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wire_name = check_hclk_src(wire_name, src_cmt)
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if wire_name is None:
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continue
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idelayctrl_in_clock_region[src_cmt] = True
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print(
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"""
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assign I_{site} = {clock_source};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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IDELAYCTRL idelay_ctrl_{site} (
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.RDY(),
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.REFCLK(I_{site}),
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.RST()
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);""".format(site=site, clock_source=wire_name))
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# Add SERDES driven by BUFH or MMCM
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for tile, site in gen_sites('ILOGICE3'):
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wire_name = None
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clock_region = site_to_cmt[site]
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if clock_region not in clock_region_limit:
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# Select serdes limit and relative location per clock region
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serdes_location = random.choice(["TOP", "BOTTOM", "ANY"])
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if serdes_location in "ANY":
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#We want TOP and BOTTOM IGCLK PIPs occupied but leave one slot for IDELAYCTRL
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if idelayctrl_in_clock_region[clock_region]:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 11
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else:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 12
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else:
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if idelayctrl_in_clock_region[clock_region]:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 5
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else:
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clock_region_limit[clock_region] = 0 if random.random(
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) < 0.2 else 6
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clock_region_serdes_location[clock_region] = serdes_location
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# We reached the limit of hclks in this clock region
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if clock_region_limit[clock_region] == 0:
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continue
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# Add a serdes if it's located at the correct side from the HCLK_IOI tile
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if clock_region_serdes_location[clock_region] not in "ANY" and \
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serdes_relative_location(tile, site) != clock_region_serdes_location[clock_region]:
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continue
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if random.random() > 0.1:
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wire_name = global_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=True)
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if wire_name is None:
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continue
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src_cmt = global_clock_sources.source_to_cmt[wire_name]
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wire_name = check_hclk_src(wire_name, src_cmt)
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if wire_name is None:
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print("//wire is None")
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continue
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clock_region_limit[clock_region] -= 1
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print(
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"""
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assign serdes_clk_{site} = {clock_source};""".format(
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site=site, clock_source=wire_name))
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else:
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wire_name = cmt_fast_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=False)
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if wire_name is None:
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continue
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src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name]
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wire_name = check_cmt_clk_src(wire_name, src_cmt)
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if wire_name is None:
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continue
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bufio_site = get_clock_region_site("BUFIO", clock_region)
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if bufio_site is None:
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continue
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print(
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"""
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assign serdes_clk_{serdes_loc} = O_{site};
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assign I_{site} = {clock_source};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFIO bufio_{site} (
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.O(O_{site}),
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.I(I_{site})
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);""".format(site=bufio_site, clock_source=wire_name, serdes_loc=site))
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print(
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"// clock_region: {} {}".format(
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clock_region, clock_region_serdes_location[clock_region]))
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{loc}" *)
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ISERDESE2 #(
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.DATA_RATE("SDR"),
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.DATA_WIDTH(4),
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.DYN_CLKDIV_INV_EN("FALSE"),
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.DYN_CLK_INV_EN("FALSE"),
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.INIT_Q1(1'b0),
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.INIT_Q2(1'b0),
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.INIT_Q3(1'b0),
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.INIT_Q4(1'b0),
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.INTERFACE_TYPE("OVERSAMPLE"),
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.IOBDELAY("NONE"),
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.NUM_CE(2),
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.OFB_USED("FALSE"),
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.SERDES_MODE("MASTER"),
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.SRVAL_Q1(1'b0),
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.SRVAL_Q2(1'b0),
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.SRVAL_Q3(1'b0),
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.SRVAL_Q4(1'b0)
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)
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ISERDESE2_inst_{loc} (
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.CLK(serdes_clk_{loc}),
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.CLKB(),
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.CLKDIV(),
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.D(1'b0),
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.DDLY(),
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.OFB(),
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.OCLKB(),
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.RST(),
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.SHIFTIN1(),
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.SHIFTIN2()
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);
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""".format(loc=site, clock_source=wire_name))
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# BUFRs
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for _, site in gen_sites('BUFR'):
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if random.random() < 0.6:
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if random.random() < 0.5:
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wire_name = luts.get_next_output_net()
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else:
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wire_name = cmt_fast_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=False)
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if wire_name is None:
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continue
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src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name]
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wire_name = check_cmt_clk_src(wire_name, src_cmt)
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if wire_name is None:
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continue
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bufr_clock_sources.add_clock_source(
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'O_{site}'.format(site=site), site_to_cmt[site])
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# Add DIVIDE
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divide = "BYPASS"
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if random.random() < 0.5:
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divide = "".format(random.randint(2, 8))
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print(
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"""
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assign I_{site} = {clock_source};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFR #(.BUFR_DIVIDE("{divide}")) bufr_{site} (
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.O(O_{site}),
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.I(I_{site})
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);""".format(site=site, clock_source=wire_name, divide=divide),
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file=bufs)
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for _, site in gen_sites('MMCME2_ADV'):
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wire_name = bufr_clock_sources.get_random_source(
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site_to_cmt[site], no_repeats=True)
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if wire_name is None:
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continue
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print(
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"""
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assign cin1_{site} = {wire_name};""".format(
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site=site, wire_name=wire_name))
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print(bufs.getvalue())
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for l in luts.create_wires_and_luts():
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print(l)
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print("endmodule")
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if __name__ == '__main__':
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main()
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