mirror of https://github.com/openXC7/prjxray.git
287 lines
8.7 KiB
Tcl
287 lines
8.7 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc write_pip_txtdata {filename} {
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puts "FUZ([pwd]): Writing $filename."
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set fp [open $filename w]
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set nets [get_nets -hierarchical]
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set nnets [llength $nets]
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set neti 0
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foreach net $nets {
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incr neti
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if {($neti % 100) == 0 } {
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puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
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}
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foreach pip [get_pips -of_objects $net] {
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set tile [get_tiles -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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close $fp
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}
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proc load_todo {} {
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set fp [open "../../todo_all.txt" r]
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# Create map of pip source to remaining destinations for that pip
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set todo_map [dict create]
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for {gets $fp line} {$line != ""} {gets $fp line} {
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set parts [split $line .]
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dict lappend todo_map [lindex $parts 2] [list [lindex $parts 0] [lindex $parts 1]]
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}
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close $fp
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return $todo_map
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}
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proc route_todo {} {
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puts "Checking TODO's"
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set todo_map [load_todo]
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set nets [get_nets]
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set todo_nets [dict create]
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set used_destinations [dict create]
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foreach net $nets {
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# Check to see if this net is one we are interested in
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set wires [get_wires -of_objects $net -filter {TILE_NAME =~ *HCLK_CMT*}]
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set is_gclk_net 0
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foreach wire $wires {
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if [regexp "HCLK_CMT_MUX_CLK_\[0-9\]+" $wire] {
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set is_gclk_net 1
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break
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}
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if [regexp "HCLK_CMT_CK_IN\[0-9\]+" $wire] {
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set is_gclk_net 1
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break
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}
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}
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if {$is_gclk_net == 0} {
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puts "$net not going to a HCLK port, skipping."
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continue
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}
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foreach wire $wires {
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set tile [lindex [split $wire /] 0]
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set wire [lindex [split $wire /] 1]
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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if { ![dict exists $todo_map $wire] } {
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continue
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}
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set dsts [dict get $todo_map $wire]
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# This net is interesting, see if it is already going somewhere we
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# want.
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set found_target 0
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foreach other_wire $wires {
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if { $found_target == 1 } {
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break
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}
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set other_wire [lindex [split $other_wire /] 1]
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if { $wire == $other_wire } {
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continue
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}
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foreach dst $dsts {
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set dst_tile_type [lindex $dst 0]
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if {$dst_tile_type != $tile_type} {
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continue
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}
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set dst_wire [lindex $dst 1]
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if { $other_wire == $dst } {
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set found_target 1
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puts "Interesting net $net already going from $wire to $other_wire."
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set_property IS_ROUTE_FIXED 1 $net
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dict set used_destinations "$tile/$dst_wire" 1
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break
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}
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}
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}
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if { $found_target == 1 } {
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# Net has an interesting
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continue
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}
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dict set todo_nets $net [list $tile $wire]
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puts "Interesting net $net (including $wire) is being rerouted."
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}
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}
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dict for {net tile_wire} $todo_nets {
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set tile [lindex $tile_wire 0]
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set wire [lindex $tile_wire 1]
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set dsts [dict get $todo_map $wire]
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puts "Rerouting net $net at $tile / $wire (type $tile_type)"
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set tile_type [get_property TILE_TYPE [get_tiles $tile]]
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set todos {}
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foreach dst $dsts {
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set dst_tile_type [lindex $dst 0]
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if {$dst_tile_type != $tile_type} {
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continue
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}
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set dst_wire [lindex $dst 1]
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set is_gclk_net 0
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if [regexp "HCLK_CMT_MUX_CLK_\[0-9\]+" $dst_wire] {
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set is_gclk_net 1
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}
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if [regexp "HCLK_CMT_CK_IN\[0-9\]+" $dst_wire] {
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set is_gclk_net 1
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}
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if {$is_gclk_net == 0} {
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continue
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}
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lappend todos $dst_wire
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}
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puts "All todos for $tile_type / $wire"
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foreach dst_wire $todos {
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puts " - $dst_wire"
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}
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route_design -unroute -nets $net
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# Find an input in the todo list that this can can drive.
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foreach dst_wire $todos {
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if { [dict exists $used_destinations "$tile/$dst_wire"] } {
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puts "Not routing to $tile / $dst_wire, in use."
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continue
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}
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puts "Attempting to route to $dst_wire for net $net."
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set target_wire [get_wires "$tile/$dst_wire"]
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set target_node [get_nodes -of_objects $target_wire]
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if {[llength $target_node] == 0} {
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error "Failed to find node for $tile/$dst_wire."
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}
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set old_nets [get_nets -of_objects $target_node]
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if { $old_nets != {} } {
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route_design -unroute -nets $old_nets
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}
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set origin_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
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set new_route [find_routing_path -to $target_node -from $origin_node]
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puts "Origin node: $origin_node"
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puts "Target wire: $target_wire"
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puts "Target node: $target_node"
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# Only need to set route to one of the destinations.
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# Router will handle the rest.
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set_property FIXED_ROUTE $new_route $net
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dict set used_destinations "$tile/$dst_wire" 1
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break
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}
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}
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}
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proc make_manual_routes {filename} {
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puts "MANROUTE: Loading routes from $filename"
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set fp [open $filename r]
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foreach line [split [read $fp] "\n"] {
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if {$line eq ""} {
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continue
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}
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puts "MANROUTE: Line: $line"
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# Parse the line
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set fields [split $line " "]
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set net_name [lindex $fields 0]
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set wire_name [lindex $fields 1]
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# Check if that net exist
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if {[get_nets $net_name] eq ""} {
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puts "MANROUTE: net $net_name does not exist"
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continue
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}
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set net [get_nets $net_name]
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# Rip it up
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set_property -quiet FIXED_ROUTE "" $net
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set_property IS_ROUTE_FIXED 0 $net
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route_design -unroute -nets $net
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# Make the route
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set nodes [get_nodes -of_objects [get_wires $wire_name]]
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set status [route_via $net_name [list $nodes] 0]
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# Failure, skip manual routing of this net
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if { $status != 1 } {
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puts "MANROUTE: Manual routing failed!"
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set_property -quiet FIXED_ROUTE "" $net
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set_property IS_ROUTE_FIXED 0 $net
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continue
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}
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puts "MANROUTE: Success!"
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-38}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-123}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-161}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1575}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1684}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-1712}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-78}]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-81}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design -directive Quick
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route_design -directive Quick
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route_todo
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make_manual_routes routes.txt
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route_design -directive Quick -preserve
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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