mirror of https://github.com/openXC7/prjxray.git
168 lines
5.1 KiB
Python
168 lines
5.1 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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from prjxray.segmaker import Segmaker
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import os
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import os.path
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def bitfilter(frame, word):
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if frame < 26:
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return False
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return True
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IOCLK_MAP = {
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'HCLK_IOI_I2IOCLK_TOP0': 'HCLK_CMT_CCIO0',
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'HCLK_IOI_I2IOCLK_TOP1': 'HCLK_CMT_CCIO1',
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'HCLK_IOI_I2IOCLK_BOT0': 'HCLK_CMT_CCIO2',
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'HCLK_IOI_I2IOCLK_BOT1': 'HCLK_CMT_CCIO3',
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}
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IOCLK_SRCS = set(IOCLK_MAP.values())
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def main():
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segmk = Segmaker("design.bits")
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tiledata = {}
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pipdata = {}
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ignpip = set()
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tile_ports = {}
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'hclk_cmt', 'hclk_cmt.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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tile_ports[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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tile_ports[tile_type].add(src)
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tile_ports[tile_type].add(dst)
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with open(os.path.join(os.getenv('FUZDIR'), '..', 'piplist', 'build',
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'hclk_cmt', 'hclk_cmt_l.txt')) as f:
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for l in f:
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tile_type, dst, src = l.strip().split('.')
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if tile_type not in pipdata:
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pipdata[tile_type] = []
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tile_ports[tile_type] = set()
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pipdata[tile_type].append((src, dst))
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tile_ports[tile_type].add(src)
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tile_ports[tile_type].add(dst)
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tile_to_cmt = {}
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cmt_to_hclk_cmt = {}
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt, tile = l.strip().split(',')
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tile_to_cmt[tile] = cmt
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if tile.startswith('HCLK_CMT'):
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cmt_to_hclk_cmt[cmt] = tile
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active_ioclks = set()
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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pip_prefix, _ = pip.split(".")
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tile_from_pip, tile_type = pip_prefix.split('/')
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assert tile == tile_from_pip
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if src in IOCLK_MAP:
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active_ioclks.add(
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(cmt_to_hclk_cmt[tile_to_cmt[tile]], IOCLK_MAP[src]))
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if not tile.startswith('HCLK_CMT'):
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continue
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if tile not in tiledata:
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tiledata[tile] = {
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"type": tile_type,
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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tiledata[tile]["pips"].add((src, dst))
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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if pnum == 1 or pdir == 0:
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ignpip.add((src, dst))
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for tile, pips_srcs_dsts in tiledata.items():
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tile_type = pips_srcs_dsts["type"]
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pips = pips_srcs_dsts["pips"]
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for src, dst in pipdata[tile_type]:
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if (src, dst) in ignpip:
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pass
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elif (src, dst) in pips:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
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elif dst not in tiledata[tile]["dsts"]:
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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for port in tile_ports[tile_type]:
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# These ones do not have any outgoing connections from the tile.
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if "FREQ_REF" in port:
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continue
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# There seems to be no special bits related to use of
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# HCLK_CMT_MUX_CLKINT_n wires.
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if "HCLK_CMT_MUX_CLKINT" in port:
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continue
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# It seems that CCIOn_USED is not enabled when a net goes through
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# FREQ_REFn. Do not emit this tag if this happens.
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if "CCIO" in port:
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n = int(port[-1])
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dst = "HCLK_CMT_MUX_OUT_FREQ_REF{}".format(n)
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if dst in tiledata[tile]["dsts"]:
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continue
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if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
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segmk.add_tile_tag(tile, "{}_USED".format(port), 1)
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else:
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segmk.add_tile_tag(tile, "{}_USED".format(port), 0)
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for ioclk in IOCLK_SRCS:
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if ioclk in tiledata[tile]["srcs"] or (tile,
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ioclk) in active_ioclks:
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segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 1)
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else:
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segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 0)
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segmk.compile(bitfilter=bitfilter)
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segmk.write()
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if __name__ == "__main__":
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main()
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