mirror of https://github.com/openXC7/prjxray.git
348 lines
9.4 KiB
Python
348 lines
9.4 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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""" Emits top.v's for various BUFHCE routing inputs. """
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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from io import StringIO
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CMT_XY_FUN = util.create_xy_fun(prefix='')
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BUFGCTRL_XY_FUN = util.create_xy_fun('BUFGCTRL_')
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def read_site_to_cmt():
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""" Yields clock sources and which CMT they route within. """
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt = l.strip().split(',')
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yield (site, cmt)
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class ClockSources(object):
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""" Class for tracking clock sources.
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Some clock sources can be routed to any CMT, for these, cmt='ANY'.
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For clock sources that belong to a CMT, cmt should be set to the CMT of
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the source.
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"""
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def __init__(self):
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self.sources = {}
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self.merged_sources = {}
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self.source_to_cmt = {}
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self.used_sources_from_cmt = {}
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def add_clock_source(self, source, cmt):
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""" Adds a source from a specific CMT.
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cmt='ANY' indicates that this source can be routed to any CMT.
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"""
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if cmt not in self.sources:
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self.sources[cmt] = []
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self.sources[cmt].append(source)
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assert source not in self.source_to_cmt or self.source_to_cmt[
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source] == cmt, source
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self.source_to_cmt[source] = cmt
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def get_random_source(self, cmt):
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""" Get a random source that is routable to the specific CMT.
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get_random_source will return a source that is either cmt='ANY',
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cmt equal to the input CMT, or the adjecent CMT.
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"""
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if cmt not in self.merged_sources:
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choices = []
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if 'ANY' in self.sources:
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choices.extend(self.sources['ANY'])
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if cmt in self.sources:
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choices.extend(self.sources[cmt])
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x, y = CMT_XY_FUN(cmt)
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if x % 2 == 0:
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x += 1
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else:
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x -= 1
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paired_cmt = 'X{}Y{}'.format(x, y)
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if paired_cmt in self.sources:
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choices.extend(self.sources[paired_cmt])
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self.merged_sources[cmt] = choices
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if self.merged_sources[cmt]:
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source = random.choice(self.merged_sources[cmt])
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source_cmt = self.source_to_cmt[source]
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if source_cmt not in self.used_sources_from_cmt:
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self.used_sources_from_cmt[source_cmt] = set()
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self.used_sources_from_cmt[source_cmt].add(source)
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if source_cmt != 'ANY' and len(
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self.used_sources_from_cmt[source_cmt]) > 14:
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print('//', self.used_sources_from_cmt)
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self.used_sources_from_cmt[source_cmt].remove(source)
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return None
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else:
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return source
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def main():
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"""
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BUFG's can be driven from:
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Interconnect
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HROW cascade
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"""
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print(
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'''
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module top();
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(* KEEP, DONT_TOUCH *)
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LUT6 dummy();
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''')
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site_to_cmt = dict(read_site_to_cmt())
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luts = LutMaker()
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wires = StringIO()
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bufgs = StringIO()
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clock_sources = ClockSources()
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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def gen_sites(desired_site_type):
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site, site_type in gridinfo.sites.items():
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if site_type == desired_site_type:
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yield tile_name, site
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for _, site in gen_sites('MMCME2_ADV'):
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mmcm_clocks = [
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'mmcm_clock_{site}_{idx}'.format(site=site, idx=idx)
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for idx in range(13)
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]
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for clk in mmcm_clocks:
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clock_sources.add_clock_source(clk, site_to_cmt[site])
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print(
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"""
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wire {c0}, {c1}, {c2}, {c3}, {c4}, {c5};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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MMCME2_ADV pll_{site} (
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.CLKOUT0({c0}),
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.CLKOUT0B({c1}),
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.CLKOUT1({c2}),
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.CLKOUT1B({c3}),
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.CLKOUT2({c4}),
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.CLKOUT2B({c5}),
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.CLKOUT3({c6}),
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.CLKOUT3B({c7}),
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.CLKOUT4({c8}),
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.CLKOUT5({c9}),
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.CLKOUT6({c10}),
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.CLKFBOUT({c11}),
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.CLKFBOUTB({c12})
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);
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""".format(
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site=site,
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c0=mmcm_clocks[0],
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c1=mmcm_clocks[1],
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c2=mmcm_clocks[2],
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c3=mmcm_clocks[3],
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c4=mmcm_clocks[4],
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c5=mmcm_clocks[5],
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c6=mmcm_clocks[6],
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c7=mmcm_clocks[7],
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c8=mmcm_clocks[8],
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c9=mmcm_clocks[9],
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c10=mmcm_clocks[10],
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c11=mmcm_clocks[11],
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c12=mmcm_clocks[12],
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))
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for _, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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print(
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"""
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wire O_{site};
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wire S1_{site};
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wire S0_{site};
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wire IGNORE1_{site};
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wire IGNORE0_{site};
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wire I1_{site};
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wire I0_{site};
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wire CE1_{site};
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wire CE0_{site};
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""".format(site=site),
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file=wires)
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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BUFGCTRL bufg_{site} (
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.O(O_{site}),
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.S1(S1_{site}),
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.S0(S0_{site}),
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.IGNORE1(IGNORE1_{site}),
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.IGNORE0(IGNORE0_{site}),
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.I1(I1_{site}),
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.I0(I0_{site}),
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.CE1(CE1_{site}),
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.CE0(CE0_{site})
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);
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""".format(site=site),
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file=bufgs)
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""" BUFG clock sources:
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2 from interconnect
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Output of BUFG +/- 1
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Cascade in (e.g. PLL, MMCM)
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"""
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CLOCK_CHOICES = (
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'LUT',
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'BUFG_+1',
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'BUFG_-1',
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'CASCADE',
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)
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def find_bufg_cmt(tile):
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if '_BOT_' in tile:
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inc = 1
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else:
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inc = -1
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loc = grid.loc_of_tilename(tile)
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offset = 1
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while True:
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gridinfo = grid.gridinfo_at_loc(
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(loc.grid_x, loc.grid_y + offset * inc))
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if gridinfo.tile_type.startswith('CLK_HROW_'):
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return site_to_cmt[list(gridinfo.sites.keys())[0]]
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offset += 1
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def get_clock_net(tile, site, source_type):
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if source_type == 'LUT':
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return luts.get_next_output_net()
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elif source_type == 'BUFG_+1':
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x, y = BUFGCTRL_XY_FUN(site)
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target_y = y + 1
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max_y = ((y // 16) + 1) * 16
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if target_y >= max_y:
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target_y -= 16
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return 'O_BUFGCTRL_X{x}Y{y}'.format(x=x, y=target_y)
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elif source_type == 'BUFG_-1':
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x, y = BUFGCTRL_XY_FUN(site)
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target_y = y - 1
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min_y = (y // 16) * 16
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if target_y < min_y:
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target_y += 16
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return 'O_BUFGCTRL_X{x}Y{y}'.format(x=x, y=target_y)
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elif source_type == 'CASCADE':
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cmt = find_bufg_cmt(tile)
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return clock_sources.get_random_source(cmt)
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else:
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assert False, source_type
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for tile, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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if random.randint(0, 1):
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print(
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"""
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assign I0_{site} = {i0_net};""".format(
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site=site,
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i0_net=get_clock_net(
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tile, site, random.choice(CLOCK_CHOICES))),
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file=bufgs)
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if random.randint(0, 1):
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print(
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"""
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assign I1_{site} = {i1_net};""".format(
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site=site,
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i1_net=get_clock_net(
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tile, site, random.choice(CLOCK_CHOICES))),
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file=bufgs)
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print(
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"""
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assign S0_{site} = {s0_net};
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assign S1_{site} = {s1_net};
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assign IGNORE0_{site} = {ignore0_net};
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assign IGNORE1_{site} = {ignore1_net};
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assign CE0_{site} = {ce0_net};
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assign CE1_{site} = {ce1_net};
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""".format(
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site=site,
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s0_net=luts.get_next_output_net(),
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s1_net=luts.get_next_output_net(),
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ignore0_net=luts.get_next_output_net(),
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ignore1_net=luts.get_next_output_net(),
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ce0_net=luts.get_next_output_net(),
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ce1_net=luts.get_next_output_net(),
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),
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file=bufgs)
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for l in luts.create_wires_and_luts():
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print(l)
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print(wires.getvalue())
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print(bufgs.getvalue())
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itr = iter(gen_sites('BUFHCE'))
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for tile, site in sorted(gen_sites("BUFGCTRL"),
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key=lambda x: BUFGCTRL_XY_FUN(x[1])):
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if random.randint(0, 1):
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_, bufhce_site = next(itr)
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print(
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"""
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(* KEEP, DONT_TOUCH, LOC = "{bufhce_site}" *)
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BUFHCE bufhce_{bufhce_site} (
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.I(O_{site})
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);""".format(
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site=site,
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bufhce_site=bufhce_site,
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))
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print("endmodule")
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if __name__ == '__main__':
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main()
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