mirror of https://github.com/openXC7/prjxray.git
110 lines
3.5 KiB
Tcl
110 lines
3.5 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc write_pip_txtdata {filename} {
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puts "FUZ([pwd]): Writing $filename."
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set fp [open $filename w]
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set nets [get_nets -hierarchical]
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set nnets [llength $nets]
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set neti 0
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foreach net $nets {
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incr neti
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if {($neti % 100) == 0 } {
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puts "FUZ([pwd]): Dumping pips from net $net ($neti / $nnets)"
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}
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foreach pip [get_pips -of_objects $net] {
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set tile [get_tiles -of_objects $pip]
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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close $fp
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}
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proc make_manual_routes {filename} {
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puts "MANROUTE: Loading routes from $filename"
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set fp [open $filename r]
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foreach line [split [read $fp] "\n"] {
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if {$line eq ""} {
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continue
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}
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puts "MANROUTE: Line: $line"
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# Parse the line
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set fields [split $line " "]
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set net_name [lindex $fields 0]
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set wire_name [lindex $fields 1]
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# Check if that net exist
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if {[get_nets $net_name] eq ""} {
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puts "MANROUTE: net $net_name does not exist"
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continue
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}
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set net [get_nets $net_name]
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# Rip it up
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set_property -quiet FIXED_ROUTE "" $net
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set_property IS_ROUTE_FIXED 0 $net
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route_design -unroute -nets $net
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# Make the route
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set nodes [get_nodes -of_objects [get_wires $wire_name]]
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set status [route_via $net_name [list $nodes] 0]
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# Failure, skip manual routing of this net
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if { $status != 1 } {
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puts "MANROUTE: Manual routing failed!"
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set_property -quiet FIXED_ROUTE "" $net
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set_property IS_ROUTE_FIXED 0 $net
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continue
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}
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puts "MANROUTE: Success!"
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {AVAL-74}]
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set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-4}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-5}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-13}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-98}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-99}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-105}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-115}]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-144}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design -directive Quick
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write_checkpoint -force design_before_route.dcp
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make_manual_routes routes.txt
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route_design -directive Quick -preserve
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_pip_txtdata design.txt
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}
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run
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