mirror of https://github.com/openXC7/prjxray.git
497 lines
12 KiB
Python
497 lines
12 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import os, random
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random.seed(int(os.getenv("SEED"), 16))
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import json
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from prjxray import util
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from prjxray import verilog
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from prjxray.db import Database
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# =============================================================================
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def gen_sites():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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tile_list = []
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for tile_name in sorted(grid.tiles()):
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if "IOB33" not in tile_name or "SING" in tile_name:
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continue
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tile_list.append(tile_name)
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get_xy = util.create_xy_fun('[LR]IOB33_')
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tile_list.sort(key=get_xy)
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for iob_tile_name in tile_list:
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iob_gridinfo = grid.gridinfo_at_loc(
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grid.loc_of_tilename(iob_tile_name))
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iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33S"][0]
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iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB33M"][0]
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top_sites = {
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"IOB": iob33m,
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"ILOGIC": iob33m.replace("IOB", "ILOGIC"),
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"IDELAY": iob33m.replace("IOB", "IDELAY"),
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}
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bot_sites = {
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"IOB": iob33s,
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"ILOGIC": iob33s.replace("IOB", "ILOGIC"),
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"IDELAY": iob33s.replace("IOB", "IDELAY"),
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}
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yield iob_tile_name, top_sites, bot_sites
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def gen_iserdes(loc):
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# Site params
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params = {
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"SITE_LOC": verilog.quote(loc),
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"USE_IDELAY": random.randint(0, 1),
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"BEL_TYPE": verilog.quote("ISERDESE2"),
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"INIT_Q1": random.randint(0, 1),
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"INIT_Q2": random.randint(0, 1),
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"INIT_Q3": random.randint(0, 1),
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"INIT_Q4": random.randint(0, 1),
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"SRVAL_Q1": random.randint(0, 1),
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"SRVAL_Q2": random.randint(0, 1),
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"SRVAL_Q3": random.randint(0, 1),
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"SRVAL_Q4": random.randint(0, 1),
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"NUM_CE": random.randint(1, 2),
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# The following one shows negative correlation (0 - not inverted)
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"IS_D_INVERTED": random.randint(0, 1),
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# No bits were found for parameters below
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"IS_OCLKB_INVERTED": random.randint(0, 1),
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"IS_OCLK_INVERTED": random.randint(0, 1),
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"IS_CLKDIVP_INVERTED": random.randint(0, 1),
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"IS_CLKDIV_INVERTED": random.randint(0, 1),
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"IS_CLKB_INVERTED": random.randint(0, 1),
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"IS_CLK_INVERTED": random.randint(0, 1),
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"DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
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"DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])),
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"IOBDELAY": verilog.quote(
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random.choice(["NONE", "IBUF", "IFD", "BOTH"])),
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"OFB_USED": verilog.quote(
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random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs
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}
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iface_type = random.choice(
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["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"])
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data_rate = random.choice(["SDR", "DDR"])
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serdes_mode = random.choice(["MASTER", "SLAVE"])
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params["INTERFACE_TYPE"] = verilog.quote(iface_type)
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params["DATA_RATE"] = verilog.quote(data_rate)
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params["SERDES_MODE"] = verilog.quote(serdes_mode)
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# Networking mode
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if iface_type == "NETWORKING":
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data_widths = {
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"SDR": [2, 3, 4, 5, 6, 7, 8],
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"DDR": [4, 6, 8, 10, 14],
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}
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params["DATA_WIDTH"] = random.choice(data_widths[data_rate])
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# Others
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else:
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params["DATA_WIDTH"] = 4
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if verilog.unquote(params["OFB_USED"]) == "TRUE":
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params["IOBDELAY"] = verilog.quote("NONE")
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return params
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def gen_iddr(loc):
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# Site params
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params = {
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"SITE_LOC":
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verilog.quote(loc),
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"USE_IDELAY":
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random.randint(0, 1),
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"BEL_TYPE":
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verilog.quote(random.choice(["IDDR", "IDDR_NO_CLK"])),
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"INIT_Q1":
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random.randint(0, 1),
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"INIT_Q2":
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random.randint(0, 1),
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"SRTYPE":
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verilog.quote(random.choice(["ASYNC", "SYNC"])),
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"DDR_CLK_EDGE":
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verilog.quote(
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random.choice(
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["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])),
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"CE1USED":
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random.randint(0, 1),
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"SR_MODE":
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verilog.quote(random.choice(["NONE", "SET", "RST"])),
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"IS_C_INVERTED":
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random.randint(0, 1),
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"IS_D_INVERTED":
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random.randint(0, 1),
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}
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if params["USE_IDELAY"]:
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params["IDELMUX"] = random.randint(0, 1)
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params["IFFDELMUX"] = random.randint(0, 1)
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else:
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params["IDELMUX"] = 0
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params["IFFDELMUX"] = 0
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return params
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def run():
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# Get all [LR]IOI3 tiles
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tiles = list(gen_sites())
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# Header
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print("// Tile count: %d" % len(tiles))
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print("// Seed: '%s'" % os.getenv("SEED"))
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print(
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'''
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module top (
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(* CLOCK_BUFFER_TYPE = "NONE" *)
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input wire clk1,
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(* CLOCK_BUFFER_TYPE = "NONE" *)
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input wire clk2,
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input wire ce,
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input wire rst,
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input wire [{N}:0] di,
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output wire [{N}:0] do
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);
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wire [{N}:0] di_buf;
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wire [{N}:0] do_buf;
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// IDELAYCTRL
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(* KEEP, DONT_TOUCH *)
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IDELAYCTRL idelayctrl();
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'''.format(**{"N": len(tiles) - 1}))
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# LOCes IOBs
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data = []
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for i, sites in enumerate(tiles):
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tile_name = sites[0]
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# Use site
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if random.randint(0, 19) > 0: # Use more often
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# Top sites
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if random.randint(0, 1):
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this_sites = sites[1]
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other_sites = sites[2]
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# Bottom sites
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else:
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this_sites = sites[2]
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other_sites = sites[1]
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# Generate cell
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bel_types = ["IDDR", "ISERDESE2"]
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bel_type = bel_types[int(
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random.randint(0, 2) > 0)] # ISERDES more often
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if bel_type == "ISERDESE2":
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params = gen_iserdes(this_sites["ILOGIC"])
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if bel_type == "IDDR":
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params = gen_iddr(this_sites["ILOGIC"])
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params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"])
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params["IS_USED"] = 1
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# Instantiate the cell
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print('')
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print('// This : ' + " ".join(this_sites.values()))
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print('// Other: ' + " ".join(other_sites.values()))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"])
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print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i))
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print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"])
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print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i))
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clk1_conn = random.choice(["clk1", ""])
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param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items())
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print(
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'ilogic_single #(%s) ilogic_%03d (.clk1(%s), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));'
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% (param_str, i, clk1_conn, i, i))
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params["CHAINED"] = 0
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params["TILE_NAME"] = tile_name
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# Params for the second site
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other_params = {
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"TILE_NAME": tile_name,
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"SITE_LOC": verilog.quote(other_sites["ILOGIC"]),
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"IDELAY_LOC": verilog.quote(other_sites["IDELAY"]),
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"IS_USED": 0,
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}
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# Append to data list
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data.append([params, other_params])
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# Don't use sites
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else:
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params_list = [
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{
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"TILE_NAME": tile_name,
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"SITE_LOC": verilog.quote(sites[1]["ILOGIC"]),
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"IDELAY_LOC": verilog.quote(sites[1]["IDELAY"]),
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"IS_USED": 0,
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},
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{
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"TILE_NAME": tile_name,
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"SITE_LOC": verilog.quote(sites[2]["ILOGIC"]),
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"IDELAY_LOC": verilog.quote(sites[2]["IDELAY"]),
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"IS_USED": 0,
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}
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]
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data.append(params_list)
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# Store params
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with open("params.json", "w") as fp:
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json.dump(data, fp, sort_keys=True, indent=1)
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print(
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'''
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endmodule
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(* KEEP, DONT_TOUCH *)
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module ilogic_single(
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input wire clk1,
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input wire clk2,
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input wire ce,
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input wire rst,
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input wire I,
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output wire O,
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input wire [1:0] shiftin,
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output wire [1:0] shiftout
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);
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parameter SITE_LOC = "";
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parameter IS_USED = 1;
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parameter BEL_TYPE = "ISERDESE2";
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parameter IDELAY_LOC = "";
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parameter USE_IDELAY = 0;
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parameter IDELMUX = 0;
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parameter IFFDELMUX = 0;
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parameter INTERFACE_TYPE = "NETWORKING";
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parameter DATA_RATE = "DDR";
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parameter DATA_WIDTH = 4;
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parameter SERDES_MODE = "MASTER";
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parameter NUM_CE = 2;
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parameter INIT_Q1 = 0;
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parameter INIT_Q2 = 0;
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parameter INIT_Q3 = 0;
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parameter INIT_Q4 = 0;
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parameter SRVAL_Q1 = 0;
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parameter SRVAL_Q2 = 0;
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parameter SRVAL_Q3 = 0;
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parameter SRVAL_Q4 = 0;
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parameter IS_D_INVERTED = 0;
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parameter IS_OCLK_INVERTED = 0;
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parameter IS_OCLKB_INVERTED = 0;
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parameter IS_CLK_INVERTED = 0;
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parameter IS_CLKB_INVERTED = 0;
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parameter IS_CLKDIV_INVERTED = 0;
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parameter IS_CLKDIVP_INVERTED = 0;
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parameter DYN_CLKDIV_INV_EN = "FALSE";
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parameter DYN_CLK_INV_EN = "FALSE";
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parameter IOBDELAY = "NONE";
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parameter OFB_USED = "FALSE";
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parameter DDR_CLK_EDGE = "OPPOSITE_EDGE";
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parameter SRTYPE = "ASYNC";
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parameter CE1USED = 0;
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parameter SR_MODE = "NONE";
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parameter IS_C_INVERTED = 0;
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wire [8:0] x;
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wire ddly;
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(* KEEP, DONT_TOUCH *)
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generate if (IS_USED && USE_IDELAY) begin
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// IDELAY
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(* LOC=IDELAY_LOC, KEEP, DONT_TOUCH *)
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IDELAYE2 idelay
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(
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.C(clk),
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.REGRST(),
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.LD(),
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.CE(),
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.INC(),
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.CINVCTRL(),
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.CNTVALUEIN(),
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.IDATAIN(I),
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.DATAIN(),
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.LDPIPEEN(),
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.DATAOUT(ddly),
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.CNTVALUEOUT()
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);
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end else begin
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assign ddly = 0;
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end endgenerate
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(* KEEP, DONT_TOUCH *)
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generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin
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// ISERDES
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(* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
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ISERDESE2 #
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(
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.INTERFACE_TYPE(INTERFACE_TYPE),
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.DATA_RATE(DATA_RATE),
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.DATA_WIDTH(DATA_WIDTH),
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.SERDES_MODE(SERDES_MODE),
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.NUM_CE(NUM_CE),
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.IS_D_INVERTED(IS_D_INVERTED),
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.IS_OCLK_INVERTED(IS_OCLK_INVERTED),
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.IS_OCLKB_INVERTED(IS_OCLKB_INVERTED),
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.IS_CLK_INVERTED(IS_CLK_INVERTED),
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.IS_CLKB_INVERTED(IS_CLKB_INVERTED),
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.IS_CLKDIV_INVERTED(IS_CLKDIV_INVERTED),
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.IS_CLKDIVP_INVERTED(IS_CLKDIVP_INVERTED),
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.INIT_Q1(INIT_Q1),
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.INIT_Q2(INIT_Q2),
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.INIT_Q3(INIT_Q3),
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.INIT_Q4(INIT_Q4),
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.SRVAL_Q1(SRVAL_Q1),
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.SRVAL_Q2(SRVAL_Q2),
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.SRVAL_Q3(SRVAL_Q3),
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.SRVAL_Q4(SRVAL_Q4),
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.DYN_CLKDIV_INV_EN(DYN_CLKDIV_INV_EN),
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.DYN_CLK_INV_EN(DYN_CLK_INV_EN),
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.IOBDELAY(IOBDELAY),
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.OFB_USED(OFB_USED)
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)
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isedres
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(
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.D(I),
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.DDLY(),
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.OFB(),
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//.TFB(),
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.CE1(),
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.CE2(),
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.DYNCLKSEL(),
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.CLK(clk1),
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.CLKB(clk2),
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.OCLK(),
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.OCLKB(),
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.DYNCLKDIVSEL(),
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.CLKDIV(),
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.CLKDIVP(),
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.RST(),
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.BITSLIP(),
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.O(x[8]),
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.Q1(x[0]),
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.Q2(x[1]),
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.Q3(x[2]),
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.Q4(x[3]),
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.Q5(x[4]),
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.Q6(x[5]),
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.Q7(x[6]),
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.Q8(x[7]),
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.SHIFTIN1(shiftin[0]),
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.SHIFTIN2(shiftin[1]),
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.SHIFTOUT1(shiftout[0]),
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.SHIFTOUT2(shiftout[1])
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);
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end else if (IS_USED && BEL_TYPE == "IDDR") begin
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// IDDR
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(* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
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IDDR #
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(
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.DDR_CLK_EDGE(DDR_CLK_EDGE),
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.INIT_Q1(INIT_Q1),
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.INIT_Q2(INIT_Q2),
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.SRTYPE(SRTYPE)
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)
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iddr
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(
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.C(clk1),
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.CE( (CE1USED) ? ce : 1'hx ),
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.D( (IFFDELMUX) ? ddly : I ),
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.S( (SR_MODE == "SET") ? rst : 1'd0 ),
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.R( (SR_MODE == "RST") ? rst : 1'd0 ),
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.Q1(x[0]),
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.Q2(x[1])
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);
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assign x[8] = (IDELMUX) ? ddly : I;
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assign x[7:2] = 0;
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end else if (IS_USED && BEL_TYPE == "IDDR_NO_CLK") begin
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// IDDR
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(* LOC=SITE_LOC, KEEP, DONT_TOUCH *)
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IDDR #
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(
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.IS_C_INVERTED(IS_C_INVERTED),
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.IS_D_INVERTED(IS_D_INVERTED),
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.DDR_CLK_EDGE(DDR_CLK_EDGE),
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.INIT_Q1(INIT_Q1),
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.INIT_Q2(INIT_Q2),
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.SRTYPE(SRTYPE)
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)
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iddr
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(
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.C(),
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.CE( (CE1USED) ? ce : 1'hx ),
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.D( (IFFDELMUX) ? ddly : I ),
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.S( (SR_MODE == "SET") ? rst : 1'd0 ),
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.R( (SR_MODE == "RST") ? rst : 1'd0 ),
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.Q1(x[0]),
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.Q2(x[1])
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);
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assign x[8] = (IDELMUX) ? ddly : I;
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assign x[7:2] = 0;
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end else begin
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assign x[0] = I;
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assign x[1] = I;
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assign x[2] = I;
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assign x[3] = I;
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assign x[4] = I;
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assign x[5] = I;
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assign x[6] = I;
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assign x[7] = I;
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assign x[8] = I;
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end endgenerate
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// Output
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assign O = |x;
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endmodule
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''')
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run()
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