mirror of https://github.com/openXC7/prjxray.git
138 lines
4.4 KiB
Tcl
138 lines
4.4 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc make_io_pin_sites {} {
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# get all possible IOB pins
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foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
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set site [get_sites -of_objects $pad]
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if {[llength $site] == 0} {
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continue
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}
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if [string match IOB33* [get_property SITE_TYPE $site]] {
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dict append io_pin_sites $site $pad
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}
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}
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return $io_pin_sites
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}
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proc load_pin_lines {} {
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# IOB_X0Y103 clk input
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# IOB_X0Y129 do[0] output
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set fp [open "$::env(SRC_DIR)/params.csv" r]
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set pin_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend pin_lines [split $line ","]
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}
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close $fp
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return $pin_lines
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}
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proc loc_pins {} {
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set pin_lines [load_pin_lines]
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set io_pin_sites [make_io_pin_sites]
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puts "Looping"
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foreach line $pin_lines {
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puts "$line"
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lassign $line site_str pin_str io cell_str
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# Have: site
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# Want: pin for site
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set site [get_sites $site_str]
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#set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
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# set port [get_ports -of_objects $site]
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set port [get_ports $pin_str]
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set tile [get_tiles -of_objects $site]
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set pin [dict get $io_pin_sites $site]
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set iostandard [get_property IOSTANDARD $port]
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD $iostandard" $port
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}
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}
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proc set_property_value_on_port {property value port} {
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set_property $property $value $port
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set got [get_property $property $port]
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if {"$got" != "$value"} {
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puts "Skipping: wanted $value, got $got"
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return 1
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}
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return 0
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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# Mostly doesn't matter since IOB are special, but add anyway
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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loc_pins
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place_design
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route_design
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set pin_lines [load_pin_lines]
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# For HR Current Drive
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set property_dictionary [dict create \
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LVCMOS12 \
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[dict create DRIVE [list 4 8 12] SLEW [list SLOW FAST]] \
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LVCMOS15 \
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[dict create DRIVE [list 4 8 12 16] SLEW [list SLOW FAST]] \
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LVCMOS18 \
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[dict create DRIVE [list 4 8 12 16 24] SLEW [list SLOW FAST]] \
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LVCMOS25 \
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[dict create DRIVE [list 4 8 12 16] SLEW [list SLOW FAST]] \
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LVCMOS33 \
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[dict create DRIVE [list 4 8 12 16] SLEW [list SLOW FAST]] \
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LVTTL \
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[dict create DRIVE [list 4 8 12 16 24] SLEW [list SLOW FAST]] \
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]
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#HSUL_12 no DRIVE support, only SLEW
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#HSTL_I, HSTL_II, HSTL_I_18, HSTL_II_18 no drive support, only SLEW
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#SSTL/18/135/ no drive support, only SLEW
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foreach iostandard [dict keys $property_dictionary] {
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foreach slew [dict get $property_dictionary $iostandard SLEW] {
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foreach drive [dict get $property_dictionary $iostandard DRIVE] {
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foreach line $pin_lines {
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lassign $line site_str pin_str io cell_str
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set port [get_ports $pin_str]
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set_property IOSTANDARD $iostandard $port
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if {$io == "input"} continue
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if {[set_property_value_on_port SLEW $slew $port]} {
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continue
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}
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if {[set_property_value_on_port DRIVE $drive $port]} {
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continue
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}
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}
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if {[catch {write_bitstream -force design_${iostandard}_${slew}_${drive}.bit} issue]} {
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puts "WARNING failed to write: $issue"
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continue
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}
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# Only write checkpoints for acceptable bitstreams
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write_checkpoint -force design_${iostandard}_${slew}_${drive}.dcp
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}
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}
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}
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}
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run
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