mirror of https://github.com/openXC7/prjxray.git
127 lines
3.7 KiB
Python
127 lines
3.7 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import random
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random.seed(0)
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import os
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import re
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from prjxray import verilog
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from prjxray import util
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# INCREMENT is the amount of additional CLBN to be instantiated in the design.
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# This makes the fuzzer compilation more robust against failures.
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INCREMENT = os.getenv('CLBN', 0)
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CLBN = 400 + int(INCREMENT)
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SLICEX, SLICEY = util.site_xy_minmax([
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'SLICEL',
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'SLICEM',
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])
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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# Rearranged to sweep Y so that carry logic is easy to allocate
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# XXX: careful...if odd number of Y in ROI will break carry
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def gen_slices():
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for slicex in range(*SLICEX):
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for slicey in range(*SLICEY):
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# caller may reject position if needs more room
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yield ("SLICE_X%dY%d" % (slicex, slicey), (slicex, slicey))
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.csv', 'w')
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f.write('module,loc,loc2\n')
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slices = gen_slices()
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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# Don't have an O6 example
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modules = ['clb_PRECYINIT_' + x for x in ['0', '1', 'AX', 'CIN']]
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loc, loc_pos = next(slices)
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while True:
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module = random.choice(modules)
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if module == 'clb_PRECYINIT_CIN':
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# Need at least extra Y for CIN extra CLB
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if loc_pos[1] >= SLICEY[1] - 1:
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continue
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loc_co = loc
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loc_ci, _pos_ci = next(slices)
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params = '.LOC_CO("%s"), .LOC_CI("%s")' % (loc_co, loc_ci)
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# Don't really care about co, but add for completeness
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paramsc = loc_ci + ',' + loc_co
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else:
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params = '.LOC("%s")' % loc
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paramsc = loc + ',' + ''
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break
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print(' %s' % module)
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print(' #(%s)' % (params))
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print(
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' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));'
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% (i, 8 * i, 8 * i))
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f.write('%s,%s\n' % (module, paramsc))
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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print(
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'''
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module clb_PRECYINIT_0 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b0), .CI());
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endmodule
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module clb_PRECYINIT_1 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b1), .CI());
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endmodule
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module clb_PRECYINIT_AX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_FIXME";
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(din[0]), .CI());
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endmodule
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module clb_PRECYINIT_CIN (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC_CO="SLICE_FIXME";
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parameter LOC_CI="SLICE_FIXME";
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wire [3:0] co;
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//Gets CI
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(* LOC=LOC_CI, KEEP, DONT_TOUCH *)
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CARRY4 carry4_co(.O(), .CO(), .DI(din[3:0]), .S(din[7:4]), .CYINIT(co[3]), .CI());
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//Sends CO
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(* LOC=LOC_CO, KEEP, DONT_TOUCH *)
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CARRY4 carry4_ci(.O(), .CO(co), .DI(din[3:0]), .S(din[7:4]), .CYINIT(1'b0), .CI());
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endmodule
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''')
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