mirror of https://github.com/openXC7/prjxray.git
96 lines
2.3 KiB
Python
96 lines
2.3 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import random
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random.seed(0)
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import os
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import re
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from prjxray import util
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from prjxray import verilog
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# INCREMENT is the amount of additional CLBN to be instantiated in the design.
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# This makes the fuzzer compilation more robust against failures.
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INCREMENT = os.getenv('CLBN', 0)
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CLBN = 600 + int(INCREMENT)
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
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['SLICEL', 'SLICEM']):
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yield site_name
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DIN_N = CLBN * 4
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DOUT_N = CLBN * 1
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ffprims = ('FDRE', )
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ff_bels = (
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'AFF',
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'A5FF',
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'BFF',
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'B5FF',
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'CFF',
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'C5FF',
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'DFF',
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'D5FF',
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)
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verilog.top_harness(DIN_N, DOUT_N)
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f = open('params.csv', 'w')
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f.write('name,loc,ce,r\n')
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slices = gen_slices()
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print(
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'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
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(DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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ffprim = random.choice(ffprims)
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force_ce = random.randint(0, 1)
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force_r = random.randint(0, 1)
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# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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loc = next(slices)
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#bel = random.choice(ff_bels)
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bel = "AFF"
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name = 'clb_%s' % ffprim
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print(' %s' % name)
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print(
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' #(.LOC("%s"), .BEL("%s"), .FORCE_CE1(%d), .nFORCE_R0(%d))'
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% (loc, bel, force_ce, force_r))
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print(
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' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));'
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% (i, 4 * i, 1 * i))
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f.write('%s,%s,%s,%s\n' % (name, loc, force_ce, force_r))
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f.close()
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print(
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'''endmodule
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// ---------------------------------------------------------------------
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''')
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print(
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'''
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module clb_FDRE (input clk, input [3:0] din, output dout);
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parameter LOC="SLICE_X16Y114";
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parameter BEL="AFF";
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parameter FORCE_CE1=0;
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parameter nFORCE_R0=1;
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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FDRE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0] | FORCE_CE1),
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.R(din[1] & nFORCE_R0),
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.D(din[2])
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);
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endmodule
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''')
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