mirror of https://github.com/openXC7/prjxray.git
92 lines
2.1 KiB
Tcl
92 lines
2.1 KiB
Tcl
# Copyright (C) 2017-2020 The Project X-Ray Authors
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc parse_csv {} {
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set fp [open "params.csv"]
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set file_data [read $fp]
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close $fp
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set file_data [split $file_data "\n"]
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set params_map [dict create]
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set is_first_line true
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foreach line $file_data {
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if { $is_first_line } {
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set is_first_line false
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continue
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}
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# Skip empty lines
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if { $line == "" } {
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continue
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}
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set parts [split $line ","]
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dict lappend params_map [lindex $parts 0] [lindex $parts 1]
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}
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return $params_map
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}
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proc route_through_delay {} {
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set params_map [parse_csv]
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set nets [get_nets]
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dict for { key value } $params_map {
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if { $value == 0 } {
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continue
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}
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foreach net $nets {
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set wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*PCIE_INT_INTERFACE*" && NAME =~ "*OUT0*"}]
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if { $wire == "" || ![regexp $key $wire] } {
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continue
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}
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set wire_parts [split $wire "/"]
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set pcie_int_tile [lindex $wire_parts 0]
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set node [get_nodes -of_object [get_tiles $pcie_int_tile] -filter { NAME =~ "*DELAY0" }]
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route_design -unroute -nets $net
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puts "Attempting to route net $net through $node."
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route_via $net [list $node]
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}
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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# Disable MMCM frequency etc sanity checks
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place_design
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route_design
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write_checkpoint -force design_pre_force_route.dcp
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route_through_delay
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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