mirror of https://github.com/openXC7/prjxray.git
161 lines
4.8 KiB
Python
161 lines
4.8 KiB
Python
#!/usr/bin/env python3
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# -*- coding: utf-8 -*-
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#
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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import os
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import random
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import itertools
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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def gen_fifos():
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['IN_FIFO']:
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if gridinfo.tile_type[-1] == 'L':
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int_grid_x = loc.grid_x + 2
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int_tile_type = 'INT_L'
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else:
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int_grid_x = loc.grid_x - 2
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int_tile_type = 'INT_R'
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int_tile_locs = [
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(int_grid_x, loc.grid_y + idx - 5) for idx in range(12)
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]
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int_tiles = []
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for int_tile_loc in int_tile_locs:
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int_gridinfo = grid.gridinfo_at_loc(int_tile_loc)
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assert int_gridinfo.tile_type == int_tile_type, (
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int_tile_loc, int_gridinfo.tile_type, int_tile_type)
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int_tiles.append(grid.tilename_at_loc(int_tile_loc))
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yield site_name, int_tiles
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def write_params(params):
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pinstr = 'tile,val\n'
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for tile, (val, ) in sorted(params.items()):
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pinstr += '%s,%s\n' % (tile, val)
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open('params.csv', 'w').write(pinstr)
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def run():
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print('''
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module top();
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''')
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params = {}
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sites = list(gen_fifos())
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N_INT = 12
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fuzz_iter = iter(util.gen_fuzz_states(len(sites) * N_INT))
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for site, int_tiles in sites:
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assert len(int_tiles) == N_INT
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int_tiles.reverse()
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bits = itertools.islice(fuzz_iter, N_INT)
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assigns = []
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# CMT_FIFO mux usage is regular with IMUX_L40 and IMUX_L42.
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#
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# INT[idx].IMUX_L40 = IN.D{idx}[1]
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# INT[idx].IMUX_L42 = IN.D{idx}[3]
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CHANNEL = [0, 1, 2, 3, 4, 5, 5, 6, 6, 7, 8, 9]
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HOLD_BIT_0 = [1, 1, 1, 1, 1, 1, 5, 5, 1, 1, 1, 1]
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TOGGLE_BIT = [3, 3, 3, 3, 3, 3, 7, 7, 3, 3, 3, 3]
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# 0 1 2 3 4 5 6 7 8 9
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WIDTH = [4, 4, 4, 4, 4, 8, 8, 4, 4, 4]
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bits_set = set()
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for idx, (int_tile, bit) in enumerate(zip(int_tiles, bits)):
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bits_set.add((CHANNEL[idx], HOLD_BIT_0[idx]))
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bits_set.add((CHANNEL[idx], TOGGLE_BIT[idx]))
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assigns.append(' // {}'.format(int_tile))
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assigns.append(
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' assign {site}_in_d{channel}[{bit}] = 0;'.format(
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site=site,
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channel=CHANNEL[idx],
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bit=HOLD_BIT_0[idx],
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))
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assigns.append(
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' assign {site}_in_d{channel}[{bit}] = {toggle_bit};'
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.format(
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site=site,
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channel=CHANNEL[idx],
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bit=TOGGLE_BIT[idx],
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toggle_bit=bit,
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))
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params[int_tile] = (bit, )
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assigns.append('')
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for channel, width in enumerate(WIDTH):
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for bit in range(width):
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if (channel, bit) not in bits_set:
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assigns.append(
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' assign {site}_in_d{channel}[{bit}] = 1;'.
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format(
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site=site,
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channel=channel,
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bit=bit,
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))
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print(
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'''
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wire [3:0] {site}_in_d0;
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wire [3:0] {site}_in_d1;
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wire [3:0] {site}_in_d2;
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wire [3:0] {site}_in_d3;
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wire [3:0] {site}_in_d4;
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wire [7:0] {site}_in_d5;
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wire [7:0] {site}_in_d6;
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wire [3:0] {site}_in_d7;
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wire [3:0] {site}_in_d8;
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wire [3:0] {site}_in_d9;
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{assign_statements}
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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IN_FIFO fifo_{site} (
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.D0({site}_in_d0),
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.D1({site}_in_d1),
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.D2({site}_in_d2),
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.D3({site}_in_d3),
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.D4({site}_in_d4),
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.D5({site}_in_d5),
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.D6({site}_in_d6),
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.D7({site}_in_d7),
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.D8({site}_in_d8),
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.D9({site}_in_d9)
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);
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'''.format(
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site=site,
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assign_statements='\n'.join(assigns),
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))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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