mirror of https://github.com/openXC7/prjxray.git
92 lines
2.7 KiB
Bash
92 lines
2.7 KiB
Bash
#!/bin/bash
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
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#
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# Use of this source code is governed by a ISC-style
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# license that can be found in the LICENSE file or at
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# https://opensource.org/licenses/ISC
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#
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# SPDX-License-Identifier: ISC
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source ../../utils/environment.sh
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set -ex
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test $# = 1
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test ! -e $1
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mkdir $1
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cd $1
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cat > design.xdc << EOT
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set_property -dict {PACKAGE_PIN $XRAY_PIN_00 IOSTANDARD LVCMOS33} [get_ports clk]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_01 IOSTANDARD LVCMOS33} [get_ports din]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_02 IOSTANDARD LVCMOS33} [get_ports dout]
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set_property -dict {PACKAGE_PIN $XRAY_PIN_03 IOSTANDARD LVCMOS33} [get_ports stb]
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set_property LOCK_PINS {I0:A1 I1:A2 I2:A3 I3:A4 I4:A5 I5:A6} \
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[get_cells -quiet -filter {REF_NAME == LUT6} -hierarchical]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells stuff]
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resize_pblock [get_pblocks roi] -add {$XRAY_ROI}
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# requires partial reconfiguration license
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#set_property HD.RECONFIGURABLE TRUE [get_cells stuff]
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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EOT
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echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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cat > design.tcl << EOT
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source "../utilities.tcl"
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create_project -force -part $XRAY_PART design design
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read_xdc design.xdc
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read_verilog ../design.v
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read_verilog ../picorv32.v
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synth_design -top top
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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puts "Writing lutdata.txt."
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set fp [open "lutdata.txt" w]
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foreach cell [get_cells -hierarchical -filter {REF_NAME == LUT6}] {
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set bel [get_property BEL \$cell]
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set loc [get_property LOC \$cell]
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set init [get_property INIT \$cell]
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puts \$fp "\$loc \$bel \$init"
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}
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close \$fp
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puts "Writing carrydata.txt."
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set fp [open "carrydata.txt" w]
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foreach cell [get_cells -hierarchical -filter {REF_NAME == CARRY4}] {
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set loc [get_property LOC \$cell]
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set cyinit_mux [get_carry_cyinit_mux_cfg \$cell]
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set di0_mux [get_carry_di0_mux_cfg \$cell]
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set di1_mux [get_carry_di1_mux_cfg \$cell]
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set di2_mux [get_carry_di2_mux_cfg \$cell]
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set di3_mux [get_carry_di3_mux_cfg \$cell]
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puts \$fp "\$loc \$cyinit_mux \$di0_mux \$di1_mux \$di2_mux \$di3_mux"
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}
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close \$fp
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EOT
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rm -rf design design.log
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${XRAY_VIVADO} -nojournal -log design.log -mode batch -source design.tcl
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#${XRAY_BITREAD} -o design_roi.bits -z -y design_roi_partial.bit
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.pgm -p design.bit
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python3 ../segdata.py
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#${XRAY_SEGMATCH} < segdata.txt > database.txt
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