mirror of https://github.com/openXC7/prjxray.git
93 lines
1.8 KiB
Verilog
93 lines
1.8 KiB
Verilog
`include "setseed.vh"
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 10;
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localparam integer DOUT_N = 10;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [9:0] din, output [9:0] dout);
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localparam integer N = 200;
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function [31:0] xorshift32(input [31:0] v);
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begin
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xorshift32 = v;
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xorshift32 = xorshift32 ^ (xorshift32 << 13);
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xorshift32 = xorshift32 ^ (xorshift32 >> 17);
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xorshift32 = xorshift32 ^ (xorshift32 << 5);
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end
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endfunction
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function [31:0] hash32(input [31:0] v);
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begin
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hash32 = v ^ `SEED;
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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hash32 = xorshift32(hash32);
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end
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endfunction
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function [63:0] hash64(input [31:0] v);
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begin
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hash64[63:32] = hash32(v);
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hash64[31: 0] = hash32(~v);
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end
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endfunction
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wire [N*10+9:0] nets;
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assign nets[9:0] = din;
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assign dout = nets[N*10+9:N*10];
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genvar i, j;
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generate
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for (i = 0; i < N; i = i+1) begin:is
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for (j = 0; j < 10; j = j+1) begin:js
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localparam integer k = i*10 + j + 10;
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wire lut_out;
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LUT6 #(
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.INIT(hash64({i, j, 8'hff}))
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) lut (
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.I0(nets[hash32({i, j, 8'h00}) % k]),
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.I1(nets[hash32({i, j, 8'h01}) % k]),
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.I2(nets[k-10]),
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.I3(nets[k-9]),
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.I4(nets[k-8]),
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.I5(nets[k-7]),
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.O(lut_out)
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);
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reg lut_out_reg;
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always @(posedge clk)
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lut_out_reg <= lut_out;
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assign nets[k] = ((i+j) % 17) < 10 ? lut_out_reg : lut_out;
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end
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end
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endgenerate
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endmodule
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