mirror of https://github.com/openXC7/prjxray.git
76 lines
2.9 KiB
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76 lines
2.9 KiB
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References
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==========
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Xilinx documents one should be familiar with:
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---------------------------------------------
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### UG470: 7 Series FPGAs Configuration User Guide
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https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
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*Chapter 5: Configuration Details* contains a good description of the overall
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bit-stream format. (See section "Bitstream Composition" and following.)
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### UG912: Vivado Design Suite Properties Reference Guide
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http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug912-vivado-properties.pdf
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Contains an excellent description of the in-memory data structures and
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associated properties Vivado uses to describe the design and the chip. The TCL
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interface provides a convenient interface to access this information.
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### UG903: Vivado Design Suite User Guide: Using Constraints
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http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug903-vivado-using-constraints.pdf
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The fuzzers generate designs (HDL + Constraints) that use many physical
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contraints constraints (placement and routing) to produce bit-streams with
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exactly the desired features. It helps to learn about the available constraints
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before starting to write fuzzers.
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### UG901: Vivado Design Suite User Guide: Synthesis
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http://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug901-vivado-synthesis.pdf
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*Chapter 2: Synthesis Attributes* contains an overview of the Verilog
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attributes that can be used to control Vivado Synthesis. Many of them
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are useful for writing fuzzer designs. There is some natural overlap
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with UG903.
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### UG909: Vivado Design Suite User Guide: Partial Reconfiguration
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https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_3/ug909-vivado-partial-reconfiguration.pdf
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Among other things this UG contains some valuable information on how to constrain a design in a way so that the items inside a pblock are strictly separate from the items outside that pblock.
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### UG474: 7 Series FPGAs Configurable Logic Block
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https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf
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Describes the capabilities of a CLB, the most important non-interconnect resource of a Xilinx FPGA.
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Other documentation that might be of use:
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-----------------------------------------
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Doc of .bit container file format:
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http://www.pldtool.com/pdf/fmt_xilinxbit.pdf
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Open-Source Bitstream Generation for FPGAs, Ritesh K Soni, Master Thesis:
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https://vtechworks.lib.vt.edu/bitstream/handle/10919/51836/Soni_RK_T_2013.pdf
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VTR-to-Bitstream, Eddie Hung:
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https://eddiehung.github.io/vtb.html
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From the bitstream to the netlist, Jean-Baptiste Note and Éric Rannaud:
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http://www.fabienm.eu/flf/wp-content/uploads/2014/11/Note2008.pdf
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Wolfgang Spraul's Spartan-6 (xc6slx9) project:
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https://github.com/Wolfgang-Spraul/fpgatools
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Marek Vasut's Typhoon Cyclone IV project:
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http://git.bfuser.eu/?p=marex/typhoon.git
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XDL generator/imported for Vivado:
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https://github.com/byuccl/tincr
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