mirror of https://github.com/openXC7/prjxray.git
34 lines
1.6 KiB
ReStructuredText
34 lines
1.6 KiB
ReStructuredText
.. _architecture_overview-label:
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Overview
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========
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.. todo:: add diagrams.
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Xilinx 7-Series architecture utilizes a hierarchical design of chainable
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structures to scale across the Spartan, Artix, Kintex, and Virtex product
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lines. This documentation focuses on the Artix and Kintex devices and omits
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some concepts introduced in Virtex devices.
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At the top-level, 7-Series devices are divided into two :term:`halves <half>`
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by a virtual horizontal line separating two sets of global clock buffers
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(BUFGs). While global clocks can be connected such that they span both sets of
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BUFGs, the two halves defined by this division are treated as separate entities
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as related to configuration. The halves are referred to simply as the top and
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bottom halves.
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Each half is next divided vertically into one or more :term:`horizontal clock
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rows <horizontal clock row>`, numbered outward from the global clock buffer
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dividing line. Each horizontal clock row contains 12 clock lines that extend
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across the device perpendicular to the global clock spine. Similar to the
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global clock spine, each horizontal clock row is divided into two halves by two
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sets of horizontal clock buffers (BUFHs), one on each side of the global clock
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spine, yielding two :term:`clock domains <clock domain>`. Horizontal clocks
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may be used within a single clock domain, connected to span both clock domains
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in a horizontal clock row, or connected to global clocks.
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Clock domains have a fixed height of 50 :term:`interconnect tiles
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<tile>` centered around the horizontal clock lines (25 above, 25
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below). Various function tiles, such as :term:`CLBs <CLB>`, are attached to interconnect
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tiles.
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