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1008 Commits

Author SHA1 Message Date
Tomasz Michalak f5ba30a81c 038-cfg: Add fuzzer for the CFG tile 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-13 07:10:18 +02:00
litghost 36af12c149
Merge pull request #933 from antmicro/016-doutmux-amc31 
Fuzzer for DOUTMUX.MC31 and DFFMUX.MC31
 2019-07-10 15:47:33 -07:00
litghost 2d13b11f13
Merge pull request #935 from litghost/more_ilogic_bits 
Expand ILOGIC fuzzer to document additional ISERDES bits.
 2019-07-10 11:21:08 -07:00
Maciej Kurc b7fc6734d2 Ran format-py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:15:28 +02:00
Maciej Kurc 1e6b85b8a8 Increased number of specimens and CLBs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:07:11 +02:00
Maciej Kurc e08ce61fbe Modified 015 to include DFFMUX.MC31 for SLICEM 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 16:06:07 +02:00
Maciej Kurc 56cb76e90f Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-10 15:06:58 +02:00
litghost 05ef773e60
Merge pull request #938 from antmicro/mmcme2-base-addr-fix 
fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances
 2019-07-09 21:14:29 -07:00
Karol Gugala b989c2fc05 fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-09 18:42:04 +02:00
Keith Rothman 280191ce0e Attempt to fix fuzzer error. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:16:45 -07:00
Keith Rothman 2a242bbd62 Expand ILOGIC fuzzer to document additional ISERDES bits. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-08 17:00:06 -07:00
Keith Rothman f92fb52576 Merge branch 'master' into add_pll_interconnect_fuzzer 2019-07-08 11:22:49 -07:00
Maciej Kurc 67dba10fb7 Modified fuzzer 016 to include DOUTMUX.AMC31 feature. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-07-08 15:39:06 +02:00
Tomasz Michalak 948a3b21cc
Merge pull request #915 from antmicro/913_hclk_ioi_baseaddress 
Calculate base addresses for HCLK_IOI3 tiles.
 2019-07-04 23:32:20 +02:00
Keith Rothman b77c47b155 Fixes for zynq7 and PLL fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman a7f5a305b9 Add 034 to fuzzer makefile. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 2728b781d1 Limit pips to the ones we care about. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:19:03 -07:00
Keith Rothman 30648d554a Complete initial PLL fuzzer. 
This solves for all unknown bits, but results in a large "IN_USE"
feature for apparently constant bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman bc822f8337 Update 032 with some fixes found during interconnect fuzzing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:58 -07:00
Keith Rothman 68ad409d23 Refactor PLL segbits to leverage known register file. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-07-03 13:18:53 -07:00
Karol Gugala 78346781ce fuzzers: 007: fix Makefile targets definitions 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 19:04:10 +02:00
Karol Gugala 28d961a650 fuzzers: routing BELs: group timings by interconn oputput 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-07-02 13:08:14 +02:00
Tomasz Michalak e096d9c172 005-tilegrid: Add HCLK_IOI base addresses calculation 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-07-01 08:58:45 +02:00
Karol Gugala 6cc614f1fb fuzzers: 007: fix BEL fuzzer Makefile 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 9658653da8 fuzzers: bel: emit routing bels timings as INTERCONN 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 03252bc46f fuzzers: 007: add gitignores 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala a99e26bbd4 fuzzers: 007: make both bels and routing-bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala cb3a2b42d7 fuzzers: 007: produce sdf files for routing bels 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala 2c1d4342b7 fuzzers: 007: format python 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Karol Gugala ec28d95604 fuzzers: 007: add routing BELs fuzzer 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-29 14:12:08 +02:00
Tomasz Michalak 36e9120fc7 Fix problem with falsely ignored PIPs 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-27 08:01:01 +02:00
litghost 5fb2153a0a
Merge pull request #889 from antmicro/875_44_clk_bufg_pips 
Fix duplicate tag in 044-clk-bufg-pips
 2019-06-26 08:31:58 -07:00
Alessandro Comodi ca6bbee193
Merge pull request #908 from antmicro/fix-bram-timing-fuzzer 
007-timing: added missing aliases for bram timing
 2019-06-26 13:00:20 +02:00
litghost b8f64484da
Merge pull request #901 from antmicro/bel-fuzzer-stabilization 
BEL fuzzer stabilization
 2019-06-25 10:43:12 -07:00
litghost 73a6bc5d77
Merge pull request #906 from antmicro/tilegrid_ioi 
Calculate base addresses for IOI tiles
 2019-06-25 10:20:06 -07:00
Tomasz Michalak 00c4672c12 fuzzers: Add 046-clk-bufg-mixed-pips fuzzer 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 18:52:00 +02:00
Tomasz Michalak 19ed8c5af8 044-clk-bufg-pips: Exclude CK_BUFG_(BOT|TOP)_R_CK_MUXED from todo list 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 18:52:00 +02:00
litghost 5845918552
Merge pull request #838 from antmicro/041_clk_hrow_pips_timeout 
041-clk-hrow-pips: Fix timeout and bit collision problems
 2019-06-25 09:18:44 -07:00
Alessandro Comodi 6476443a52 007-timing: added missing aliases for bram timing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-06-25 17:13:44 +02:00
Tomasz Michalak 86164fdc18 005-tilegrid: propagate IOI SING and Y9 tiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 12:12:37 +02:00
Tomasz Michalak 9fb26b6915 005-tilegrid: calculate IOI base address 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 11:32:32 +02:00
Karol Gugala f6450b72b8 fuzzers: 007: bel: sort timing keywords 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:48 +02:00
Karol Gugala a560cc3500 fuzzers: 007: bel: do not copy timing data 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:05 +02:00
Karol Gugala 7821cb743c fuzzers: 007: refactor bel properties handling 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:27:26 +02:00
Karol Gugala b4634413da fuzzers: 007: bel: use functions for searching in speed_model 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:25:37 +02:00
Keith Rothman 29210f81da Add empty defaults for additional new database files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-20 09:39:41 -07:00
Keith Rothman 01a0be3162 Add support to zero db to support simple groups. 
Previously these kinds of zero groups would require encoding the
final bits, rather than tags.  This is extends the dbfixup to
construct groups via groups of tags, rather than groups of bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-19 14:46:39 -07:00
Tomasz Michalak 8c059c627b int_maketodo.py: Replace assertion with warning if PIP can't be balanced 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:40 +02:00
Tomasz Michalak 5831cf604f fuzzers: Re-enable fuzzer 041-clk-hrow-pips 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00
Tomasz Michalak 2814254cbf 041-clk-hrow-pips: Balance todo list 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00