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Author SHA1 Message Date
Dr Jonathan Richard Robert Kimmitt a8de0afdb3 virtex7: HP-bank glue codified end-to-end + open-flow validation 
The open-flow (Yosys → nextpnr-xilinx → FASM → bitstream) now produces
silicon-functional bits on VC707 xc7vx485tffg1761-2 for:
  - rst_to_led (IBUF↔OBUF passthrough)
  - counter_skewfree (button-clocked 8b counter, general routing)
  - counter_sw_bufr (button → BUFR → 8b counter)
  - counter_bufr  (200 MHz LVDS sysclk → IBUFDS → BUFR → 8b counter)
  - counter_2bufg (2× BUFGCTRL on the same source)
  - vc707_telegraph (125 MHz crystal → IBUFDS_GTE2 → BUFG → UART smoke test)
  - vc707_picosoc  (picorv32 + simpleuart + BRAM @ 125 MHz; UART prints
                    'PicoSoC alive on VC707 @ 125 MHz' on /dev/ttyUSB0)

Highlights of this drop:

utils/fasm2frames.py (+223 net):
  - Bank-glue auto-injection for HP-bank IOB18 — IBUF/OBUF (Y0+Y1) +
    IBUFDS differential pair. Fires off the FASM-level direction
    heuristic (.IN/.IN_ONLY/IBUFDISABLE for IBUF, .DRIVE. for OBUF,
    .IN_DIFF for IBUFDS; .SLEW. is unreliable as a marker — gets emitted
    on default-state IOBs too).
  - INT_L_X32Y49 DCI cascade / bank-active markers when any LIOB18_X81
    Y1 OBUF is present.
  - PUDC_B emission rewritten for HP-bank IOSTANDARDs (10 features
    cover Y0 + Y1 default-state; all 9 historic 'PUDC_B glue' bits
    flow naturally from the existing IOSTANDARD segbits).
  - HCLK_L per-BUFRCLK-channel 'active' marker — currently codified
    for BUFRCLK3 (the channel exercised by counter_sw_bufr).
  - GFAN T-tie root glue — INT_L_X62Y(N+10).GFAN_TIE_ROOT_GLUE when
    INT_L_X62Y(N).GFAN0.GND_WIRE appears (OBUF.T → GND routing).
  - PUDC_B tile excluded from the bank-glue walk (its IN features are
    virtual; injecting OBUF_HP_BANK_GLUE on it produces spurious bits).

utils/utils.tcl (+47):
  - write_pip_txtdata bulk-fetch — replaces per-net foreach pip with
    bulk get_pips + bulk get_property IS_DIRECTIONAL + cached
    dst_wire_to_num_pips. ~4× speed-up on xc7vx485t (per-spec time on
    041-clk-hrow-pips / 045-hclk-cmt-pips drops from ~1.5 h to ~25 min).

utils/mergedb.sh (+15):
  - LIOI / LIOI_TBYTESRC / LIOI_TBYTETERM / LIOB18 / mask_liob18 sed
    rewrites for the L-side IOI/IOB18 tiles on HP-only parts (xc7vx485t
    uses left-side IOB18 too; upstream kintex7 mergedb only knew the
    right side).

11 fuzzers patched for virtex7 readiness:
  - 030-iob18 Makefile: split DB target for virtex7 (HP-only); the BUFR
    HP-bank results come from the actual fuzzer rather than HR-side sed.
  - 037-iob18-pips: L-side mirror tiles (LIOI / LIOI_TBYTESRC /
    LIOI_TBYTETERM) added to segdata glob; *_SING tiles excluded;
    EXCLUDE_RE updated for L-side prefixes.
  - 039-hclk-config: split virtex7 vs kintex7 (HCLK_IOI vs HCLK_IOI3);
    XRAY_IOSTANDARD env var; IOB18M/IOB33M alternation.
  - 047a-hclk-idelayctrl-pips: accepts both HCLK_IOI and HCLK_IOI3.
  - 041, 045, 034, 034b, 043, 044, 046: removed local
    write_pip_txtdata override that shadowed the patched utils.tcl
    bulk-fetch (was re-introducing the slow per-net Tcl path).

README.md (+86):
  - 'Virtex-7 Port Status (virtex7-support branch)' section —
    achievements, goals, work-in-progress, constraints.

Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
 2026-05-29 10:13:53 +01:00
Jonathan Kimmitt 42eddb9b9e Experimental support for xc7k325t 
Signed-off-by: Jonathan Kimmitt <jonathan@kimmitt.uk>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2024-10-25 10:11:38 +07:00
Hans Baier ee5ffe2333 add kintex 480T support 
Signed-off-by: Hans Baier <hansfbaier@gmail.com>
 2024-10-25 09:58:45 +07:00
Hans Baier b210947cb2 sort fuzzers/074-dump_all/ignored_wires/kintex7/xc7k160tffg676-2_ignored_wires.txt 
Signed-off-by: Hans Baier <hansfbaier@gmail.com>
 2024-01-08 14:00:20 +07:00
Hans Baier f4610817d4 XC7K160T: add ignored wires 
Signed-off-by: Hans Baier <hansfbaier@gmail.com>
 2024-01-08 14:00:20 +07:00
Alessandro Comodi 2eb77e4663 fuzzers: fix clean in parts fuzzers 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2022-03-03 12:50:33 +01:00
Steve f3474a2625 Add support for xc7s50 
The previous xc7s50t branch was messed up. This new branch is created to re-submit xc7s50t's changes for merging.

Signed-off-by: Steve <steve.bohan.liu@outlook.com>
 2021-12-13 18:39:27 +08:00
Daniel Schultz e60b0d5875 fuzzers: Deploy fabric data to a separate dir 
Fabric data should be deployed to a separate directory inside the database
and all devices with the same fabric should access it.

Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
 2021-01-12 22:36:58 +01:00
Keith Rothman 3abb90f2b5 Add comments to new scripts. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-10-26 13:26:26 -07:00
Keith Rothman d117b73b18 Add node names to database. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-10-26 09:32:52 -07:00
Tomasz Michalak c66f4f4aa1 Add license headers to tcl files 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 0357b3e4b1 Fix formatting after updating license headers 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 300bc62227 Add licensing header to bash scripts 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 159d6a8e88 Add licensing header to Makefiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 950d7534ec Add licensing header to fuzzers' python scripts 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tim Callahan d9ad4a74da Sort ignored wires for xc7a100t part. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2020-04-28 16:00:04 -07:00
Tim Callahan 7b4cb853d7 Enable xc7100t part db generation, add ignored wires for fuzzer 074. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2020-04-28 15:58:35 -07:00
Keith Rothman 9e21e951c8 Fix remap on new 074 code. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-21 13:01:30 -08:00
Keith Rothman 89bc2008d8 Some more fixes around ignored tiles within a grid. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-20 11:33:12 -08:00
Keith Rothman 850d16fa02 Don't clobber other parts build directories on run target. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 9f839a7a08 Attempt to parallelize 074 for additional parts. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 44b79e1e85 Remap some timing models. 
This is an approximation, but it may work better.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:08 -08:00
Keith Rothman 2bc72b5cce Increase number of processes allowed to run during final grid reduction. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:33:32 -08:00
Keith Rothman 4691ba3183 Remove temp files after 074 completes. 
- Remove unused imports.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 3f435ea30b 074-dump_all: fix bug when annotating wires speed model 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 43699a09ac 074-dump_all: fix bug in site pin delay addition 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 1257f9f855 074-dump_all: remove speed_index from tile_types 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi a2120b529e 074-dump_all: direct speed model tmp files to specimen directory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 1004ad6633 074-dump_all: get vivado exec path from env variable 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 46c28ccb91 074-dump_all: continue if site_pin is NoneType 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 986ca05686 074-dump_all: remove unnecessary lines from jobtiles.tcl 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi c16b1233d5 074-dump_all: back annotation added to tile types 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi a3b8e56194 074-dump_all: added creation of json speed model file for backannotation 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi ce35c7c37c 074-dump_all: annotate only speed model index 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Keith Rothman 445934140e Fix up some comments. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 15:15:59 -08:00
Keith Rothman f7e3442f74 Remap some timing models. 
This is an approximation, but it may work better.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 09:27:12 -08:00
Keith Rothman 9aec0c8d9c Sort wire pairs using extract_numbers. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 09:11:03 -08:00
Keith Rothman 222eefcece Use extract_numbers for sort keys to preserve previous DB output. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-18 10:45:22 -08:00
Keith Rothman 89761c1102 Add some sorting to JSON outputs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-18 06:39:20 -08:00
Keith Rothman 7dfd4adaa8 Remove xjson from 074. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-12 14:43:15 -08:00
Alessandro Comodi 5a8e10bba6 zynq: sorted and renamed ignored_wires in 074-dump_all fuzzer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 11:26:55 +01:00
Alessandro Comodi 895612c264 zynq: Add ignored wires for Zynq 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 10:21:38 +01:00
Alessandro Comodi 5ae155fd9c copy tileconn.json in the correct diretory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 117f3e51b2 revert 074 and 072 to use previous Makefile configuration 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 15d914f2c5 074-dump_all: changed ignored_wires location 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 9a88b77620 run make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e464172e03 074-dump_all: exclude tiles and node that are in the excluded roi 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 070931ec6e 074-dump_all: fix tilegrid location 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 3865c726f2 074-dump_all: increase jobs and tiles per job 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-26 10:04:52 +01:00