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2342 Commits

Author SHA1 Message Date
Maciej Kurc 4d6f75e8ad Added packing tests for SRL32+LUT6 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:27 +02:00
Maciej Kurc 98bcd3f447 Added full vivado flow to the Makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-28 10:53:22 +02:00
Maciej Kurc 4c2b0a5395 Added minitests for SRLs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-27 15:13:18 +02:00
Alessandro Comodi ca6bbee193
Merge pull request #908 from antmicro/fix-bram-timing-fuzzer 
007-timing: added missing aliases for bram timing
 2019-06-26 13:00:20 +02:00
litghost b8f64484da
Merge pull request #901 from antmicro/bel-fuzzer-stabilization 
BEL fuzzer stabilization
 2019-06-25 10:43:12 -07:00
litghost 73a6bc5d77
Merge pull request #906 from antmicro/tilegrid_ioi 
Calculate base addresses for IOI tiles
 2019-06-25 10:20:06 -07:00
litghost 87a51b96bb
Merge pull request #883 from antmicro/litex_minitest2 
Litex SoC minitest (sources)
 2019-06-25 09:28:26 -07:00
litghost 5845918552
Merge pull request #838 from antmicro/041_clk_hrow_pips_timeout 
041-clk-hrow-pips: Fix timeout and bit collision problems
 2019-06-25 09:18:44 -07:00
litghost bc3fcb0db2
Merge pull request #900 from litghost/extend_zero_db_features 
Add support to zero db to support simple groups.
 2019-06-25 09:02:10 -07:00
Alessandro Comodi 6476443a52 007-timing: added missing aliases for bram timing 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-06-25 17:13:44 +02:00
Tomasz Michalak 86164fdc18 005-tilegrid: propagate IOI SING and Y9 tiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 12:12:37 +02:00
Tomasz Michalak 9fb26b6915 005-tilegrid: calculate IOI base address 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-25 11:32:32 +02:00
Maciej Kurc 68c810ce3b Added source files dependencies to Makefiles 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-25 10:14:20 +02:00
Karol Gugala f6450b72b8 fuzzers: 007: bel: sort timing keywords 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:48 +02:00
Karol Gugala a560cc3500 fuzzers: 007: bel: do not copy timing data 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:28:05 +02:00
Karol Gugala 7821cb743c fuzzers: 007: refactor bel properties handling 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:27:26 +02:00
Karol Gugala b4634413da fuzzers: 007: bel: use functions for searching in speed_model 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-21 17:25:37 +02:00
Keith Rothman 29210f81da Add empty defaults for additional new database files. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-20 09:39:41 -07:00
Keith Rothman 816c87a393 Do not require zero features to have zero bits, but do ignore them. 
During database building, zero features may have other bits.  For now,
ignore the fact that zero features have non-zero bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-20 09:38:47 -07:00
Keith Rothman 01a0be3162 Add support to zero db to support simple groups. 
Previously these kinds of zero groups would require encoding the
final bits, rather than tags.  This is extends the dbfixup to
construct groups via groups of tags, rather than groups of bits.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-06-19 14:46:39 -07:00
Karol Gugala 0548c105e4
Merge pull request #897 from antmicro/clean-007 
Fuzzers: 007-timings: remove unused code
 2019-06-19 21:06:26 +02:00
Tomasz Michalak 8c059c627b int_maketodo.py: Replace assertion with warning if PIP can't be balanced 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:40 +02:00
Tomasz Michalak 5831cf604f fuzzers: Re-enable fuzzer 041-clk-hrow-pips 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00
Tomasz Michalak 2814254cbf 041-clk-hrow-pips: Balance todo list 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00
Tomasz Michalak 678f915467 041-clk-hrow-pips: Don't solve fake features 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-06-19 11:11:20 +02:00
Karol Gugala d5dc09948a fuzzers: 007: remove unused code 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-19 10:53:19 +02:00
Maciej Kurc 64a05b4fa2 Changed makefiles to use XRAY_DIR 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-19 09:19:28 +02:00
Karol Gugala 0f37f0c294
Merge pull request #857 from antmicro/fuzzer_007_ff_sr_to_q 
Fixed fuzzer 007 to make it extract missing timings for FFs
 2019-06-19 08:15:45 +02:00
Karol Gugala 0fe609353e fuzzers: 007: update docstring for find_aliased_pin 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 2d26781992 fuzzers: 007: tim2json: update docstrings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 37626d75e5 fuzzers: 007: fixup_timings: update docstrings 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 9b04747da9 fuzzers: 007: bel: add README 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala afb0cc78da fuzzers: 007: add docstring and assert to line_fixup function 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 63e6d17b50 fuzzers: 007: rename pin alias property -> is_property_related 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala bb9bc7bfdd fuzzers: 007: refactor aliased pins detection 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 26614e5ed4 fuzzers: 007: restore missing continue 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala c9d661d161 fuzzers: 007: run make format 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 73979fdf04 fuzzers: 007: handle pin/pin and pin/prop aliases 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala b122f07896 fuzzers: 007: do not emit clk -> clk timing checks 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 209240e77f fuzzers: 007: handle output vector pins 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala cdcb759299 fuzzers: 007: remove commented code 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 83657adbb9 fuzzers: 007: fix clock inputs inferring 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala ecb4fa1289 fuzzers: 007: use timings fixup 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Karol Gugala 91e7f3910e fuzzers: 007: add timings_fixup script 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 8366e324af Code refactoring. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc d05945ff81 Added support for aliases of pins with underscore in names. Added doctests 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 58898bb29f Removed explicit bel suffix map. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 6e1efd4815 Fixed formatting 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
Maciej Kurc 4a117330f2 Fixed fuzzer 007 so it can correctly extract SR -> Q timings in FF_INIT and REG_INIT_FF 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-06-18 18:30:48 +02:00
litghost e984015c45
Merge pull request #888 from antmicro/874_pip_seed 
050-pip-seed: Don't solve BYP_ALT|IMUX.LOGIC_OUTS_ bits
 2019-06-18 09:28:29 -07:00