13 Commits

Author	SHA1	Message	Date
Keith Rothman	e17f9e8140	Refactor routines to read pins, props, and site pins. ... Also fix Makefile intermediate. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>	2020-02-11 20:38:27 -08:00
Karol Gugala	10e022140e	fuzzers: 007: reorganize Makefiles ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-07-23 14:49:45 +02:00
Karol Gugala	78346781ce	fuzzers: 007: fix Makefile targets definitions ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-07-02 19:04:10 +02:00
Karol Gugala	6cc614f1fb	fuzzers: 007: fix BEL fuzzer Makefile ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-06-29 14:12:08 +02:00
Karol Gugala	a99e26bbd4	fuzzers: 007: make both bels and routing-bels ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-06-29 14:12:08 +02:00
Karol Gugala	ecb4fa1289	fuzzers: 007: use timings fixup ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-06-18 18:30:48 +02:00
Maciej Kurc	58898bb29f	Removed explicit bel suffix map. ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>	2019-06-18 18:30:48 +02:00
Maciej Kurc	4a117330f2	Fixed fuzzer 007 so it can correctly extract SR -> Q timings in FF_INIT and REG_INIT_FF ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>	2019-06-18 18:30:48 +02:00
Maciej Kurc	306b40eebb	Changed all scripts to use explicitly python3 ... Signed-off-by: Maciej Kurc <mkurc@antmicro.com>	2019-05-24 15:05:53 +02:00
Karol Gugala	e1440a56b4	fuzzers: 007: add properties names mappings ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-05-16 14:52:58 +02:00
Karol Gugala	634ca791c7	fuzzers: 007: bel: merge slicel and slicem timigs ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-04-28 18:53:06 -07:00
Karol Gugala	69cc63ea81	utils: add sdfmerge tool ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-04-28 18:53:06 -07:00
Karol Gugala	5d9da26f78	Fuzzers: 007: add bel timing fuzzer ... Signed-off-by: Karol Gugala <kgugala@antmicro.com>	2019-04-28 18:53:06 -07:00