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1441 Commits

Author SHA1 Message Date
Maciej Kurc 144eda40e5 Added licensing and encoding info 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 13:05:09 +02:00
Maciej Kurc 64b2075485 Fixes 035b feature prefixes, added tag grouping 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 12:48:34 +02:00
Maciej Kurc 6396c941af Fixed fuzzer dependency. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 3ee95542b8 Enabled 035b in Makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc d83a7031e5 Code formatting. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc e68b3083d4 Added changing of clock inverters / updated bits.dbf 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc ebf88a8430 Disabled renaming ILOGIC to IOB, code formatting. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc b02c0f5135 Removed aliasing with some PIP bits. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 01c1b0e23c Added filtering of some overlapping bits (by frame idx). Executing logic put in a function. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 10a6547252 Ran make format-py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 2b87eec19a Added more bits to dbf, added varying of inverters for ISERDES 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 3ad85e0e49 Fixed solution for ZINV_D 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc d3b6566206 Modified dbf file, changed some probabilities. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc f6aecf0d88 A lot of modifications and fixups. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 40d3cb5588 Added fuzzing of IDDR along with ISERDES 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 44085d34d4 Moved SDR/DDR out of width setting 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc ea0fd9eb8e Added fuzzing for chained ISERDES 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc 369aa38c6a Ran make format-py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Maciej Kurc a2552bf478 Initial fuzzer for ISERDES only. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-07-17 11:58:42 +02:00
Robert Winkler 996bcfd7a1 Adjust 032-cmt-pll fuzzer for A100T device 
This commit allows the 032-cmt-pll fuzzer to find the bits
that disappeared after changing the main fuzzed device from A50T to A100T.

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-07-16 00:04:50 +02:00
Andrew Butt 2f03a575e2 Fix SDF generation 
Signed-off-by: Andrew Butt <butta@seas.upenn.edu>
 2020-07-08 10:55:20 -04:00
Tomasz Michalak c66f4f4aa1 Add license headers to tcl files 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak fbf4dd897d Add or fix license header 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 0357b3e4b1 Fix formatting after updating license headers 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 300bc62227 Add licensing header to bash scripts 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 159d6a8e88 Add licensing header to Makefiles 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
Tomasz Michalak 950d7534ec Add licensing header to fuzzers' python scripts 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
 2020-05-26 07:33:12 -07:00
litghost 8df6ed1131
Merge pull request #1324 from antmicro/sstl15 
SSTL15 features
 2020-05-08 08:09:44 -07:00
Maciej Kurc 82e9a75dc3 Modified 030 to emit tags for SSTL15 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-05-07 13:38:14 +02:00
Maciej Kurc 317f8691f7 Disabled emission of HCLK_CMT_MUX_CLKINT_n_USED tags. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-05-04 09:19:10 +02:00
Maciej Kurc 08e8d1b118 Fixed solution of CCIOn_USED bits. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-05-04 09:16:14 +02:00
Maciej Kurc f28684c636 Fixed a bug in makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-05-04 09:16:14 +02:00
Maciej Kurc dedbfaa301 Code formatting. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-05-04 09:16:14 +02:00
Maciej Kurc f6dd2c1e7c Enhance 045 to solve FREQ_REF related PIPs 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-05-04 09:16:14 +02:00
Tim Callahan d9ad4a74da Sort ignored wires for xc7a100t part. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2020-04-28 16:00:04 -07:00
Tim Callahan 7b4cb853d7 Enable xc7100t part db generation, add ignored wires for fuzzer 074. 
Signed-off-by: Tim Callahan <tcal@google.com>
 2020-04-28 15:58:35 -07:00
litghost 895c280909
Merge pull request #1308 from antmicro/reenable_ilogic_clkb_imux22 
Re-enable IOI_ILOGIC[01]_CLKB.IOI_IMUX22_[01] pips.
 2020-04-28 11:19:25 -07:00
Maciej Kurc 28ddeb2feb Added forced routing through IMUX PIPs. Changed some stimulus. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-04-28 12:45:45 +02:00
Maciej Kurc 906bae2b31 Changed P&R directive to "quick" 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-04-24 10:12:33 +02:00
Maciej Kurc 3d44405216 Re-enabled 037 to fuzz IOI_ILOGIC[01]_CLKB\.IOI_IMUX22_[01] pips. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-04-21 18:44:41 +02:00
David Shah b757da0148 fuzzers: Add missing B-side IN_DIFF bits 
Signed-off-by: David Shah <dave@ds0.me>
 2020-03-30 17:01:48 +01:00
Tim Ansell 85ccaa09b4
Merge pull request #1257 from antmicro/docs_fix_warnings 
Fix warnings in documentation
 2020-03-18 15:19:41 -07:00
Keith Rothman 465fd4731d Add prohibited site list to tilegrid. 
Prohibited sites are sites that Vivado will not place at.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-03-13 15:21:43 -07:00
Robert Winkler 675af0728c Fix warnings in documentation 
This commit resolves all warnings in the project documentation

Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
 2020-03-11 10:32:04 +01:00
Keith Rothman 8964ad3b53 Convert CLB/CLB_INT tilegrid fuzzer to workaround prohibited locations. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-03-09 13:47:03 -07:00
Keith Rothman 9e21e951c8 Fix remap on new 074 code. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-21 13:01:30 -08:00
Keith Rothman 89bc2008d8 Some more fixes around ignored tiles within a grid. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-20 11:33:12 -08:00
Keith Rothman 22e1a8f7c3 Refactor how part specific for part generic fuzzers are marked. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:55:53 -08:00
Keith Rothman 44eb914f8d Fill holes in excluded part of grid. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman fabae5eb64 Fix some bugs in makefile work tracking. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 1f22d60160 Fix up Makefile dependences. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman bc00250f90 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman e626994d4d Add some samples for cfg_int to remove discrepancies. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 61d4a43b3f Remove some unused targets from fuzzaddr/common.mk 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 6a50598cdc Sort tilegrid_tdb.json for better debugging. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 32833e6f93 Add diagnostic to find 005 instability. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:12 -08:00
Keith Rothman 850d16fa02 Don't clobber other parts build directories on run target. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman d6e4c28323 Report full untruncated log upon failure. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 63ab362d2a Fix clean step update for 073. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 3aeb1f120a Also clean log directories. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman ec6b1aa02d Fix some typo's. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman f4fd84625f Add part to run_fuzzer output. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 80add259ed Fix some parallelism issues. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 9f839a7a08 Attempt to parallelize 074 for additional parts. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:11 -08:00
Keith Rothman 44b79e1e85 Remap some timing models. 
This is an approximation, but it may work better.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:34:08 -08:00
Alessandro Comodi 073c976128 cleaning fuzzers before running roi_only target commands 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Keith Rothman 2bc72b5cce Increase number of processes allowed to run during final grid reduction. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:33:32 -08:00
Keith Rothman 4691ba3183 Remove temp files after 074 completes. 
- Remove unused imports.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 3f435ea30b 074-dump_all: fix bug when annotating wires speed model 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 43699a09ac 074-dump_all: fix bug in site pin delay addition 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 1257f9f855 074-dump_all: remove speed_index from tile_types 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi b24f5f5ad3 fuzzers: clean and do make fuzzer/run.ok when generating part_only 
This is necessary to have a clean output when building extra-parts

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi a2120b529e 074-dump_all: direct speed model tmp files to specimen directory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 1004ad6633 074-dump_all: get vivado exec path from env variable 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 46c28ccb91 074-dump_all: continue if site_pin is NoneType 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi 986ca05686 074-dump_all: remove unnecessary lines from jobtiles.tcl 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:33:32 -08:00
Alessandro Comodi c16b1233d5 074-dump_all: back annotation added to tile types 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi a3b8e56194 074-dump_all: added creation of json speed model file for backannotation 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi ce35c7c37c 074-dump_all: annotate only speed model index 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
Alessandro Comodi 194cc230f1 fix possible concurrency issue 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-02-19 16:32:33 -08:00
litghost 84b1457b88
Merge pull request #1238 from litghost/remap_some_timing 
Remap some timing
 2020-02-19 16:31:44 -08:00
Keith Rothman 445934140e Fix up some comments. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 15:15:59 -08:00
Keith Rothman f7e3442f74 Remap some timing models. 
This is an approximation, but it may work better.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 09:27:12 -08:00
Keith Rothman 9aec0c8d9c Sort wire pairs using extract_numbers. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-19 09:11:03 -08:00
Keith Rothman 222eefcece Use extract_numbers for sort keys to preserve previous DB output. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-18 10:45:22 -08:00
litghost 66916fb787
Merge pull request #1245 from antmicro/fix_1234 
Fix for the lost IOB bits
 2020-02-18 09:58:46 -08:00
litghost c0289c5948
Merge pull request #1186 from antmicro/in_term_group 
Grouping of IN_TERM features
 2020-02-18 09:20:31 -08:00
Keith Rothman 89761c1102 Add some sorting to JSON outputs. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-18 06:39:20 -08:00
Maciej Kurc 9183126bdd Fixed the 030 fuzzer to automatically detect where the PUDC_B site is. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-18 12:01:02 +01:00
litghost 541d88c999
Merge pull request #1229 from litghost/serdes_timing 
I/OSERDES BEL timing
 2020-02-13 07:41:43 -08:00
Maciej Kurc 014462de26 Ported tag grouping to dbfixup.py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-13 13:47:32 +01:00
Tim Ansell db14b30fdb
Merge pull request #1230 from litghost/sorting-fix 
Copy of #1226, remove use of xjson from `074`

>  - Rework how the `json` files are sorted (numbers are treated as numerics).
>  - Sort `csv` and `txt` files.
>  - Sort `segbits.*origin_info.db` files.
>  - Sort the grid file.
> 
> How this changes the output can be seen in https://github.com/SymbiFlow/prjxray-db/pull/11/files
 2020-02-12 19:26:08 -08:00
Keith Rothman 7dfd4adaa8 Remove xjson from 074. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-12 14:43:15 -08:00
Keith Rothman 49b5a8cde6 Handle weird bel pins that aren't really clocks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-12 12:59:14 -08:00
Keith Rothman 2f388235e4 Update doctests. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:55:07 -08:00
Keith Rothman ec69db772d Remove progressbar 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:50:50 -08:00
Keith Rothman 0c1a404ab1 Run make format. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:49:09 -08:00
Keith Rothman 564863ccad Refactor remaining function in tim2json.py 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:38:34 -08:00
Keith Rothman e17f9e8140 Refactor routines to read pins, props, and site pins. 
Also fix Makefile intermediate.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 20:38:27 -08:00
Keith Rothman b9f8f962f1 Start of SERDES timing. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-11 16:52:12 -08:00
Maciej Kurc 1196f67f71 Moved the group.py script to the utils dir. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-11 12:24:34 +01:00
Maciej Kurc b20bae5341 Added grouping of IN_TERM features so they can be decoded unambigosly. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-02-11 12:24:34 +01:00
Keith Rothman 2678e7a3a7 Handle both jobserver-fds and jobserver-auth flags. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2020-02-10 14:50:46 -08:00
Tomasz Michalak de763a309c fuzzers: Add support for KiB, MiB and GiB units 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2020-01-29 12:33:13 +01:00
Maciej Kurc 45338f1af4 Reworked the PS7 port def. extractor so instead of a minitest its now a fuzzer. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2020-01-28 12:17:16 +01:00
litghost 3f0804a417
Merge pull request #1162 from antmicro/zynq_7020_tilegrid 
Tilegrid generation for Zynq 7020
 2020-01-27 19:24:07 -08:00
litghost e7667a8daf
Merge pull request #1212 from daveshah1/dspimprove 
fuzzers: Improve DSP fuzzer
 2020-01-27 07:18:21 -08:00
Alessandro Comodi 31cfa88344 generate both xc7010 and xc7020 parts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 11:26:55 +01:00
Alessandro Comodi 5a8e10bba6 zynq: sorted and renamed ignored_wires in 074-dump_all fuzzer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 11:26:55 +01:00
Tomasz Michalak ecab15cd39 zynq: 034-cmt-pll-pips: Remove Zynq specific workarounds 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2020-01-27 11:26:55 +01:00
David Shah 22213404a5 fuzzers: Improve DSP fuzzer 
Signed-off-by: David Shah <dave@ds0.me>
 2020-01-27 09:27:46 +00:00
Alessandro Comodi 895612c264 zynq: Add ignored wires for Zynq 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 10:21:38 +01:00
Alessandro Comodi b211908e26 zynq: fuzzers: Remove Zynq specific workarounds 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 10:21:38 +01:00
Alessandro Comodi fb26896dcb zynq: Allow LIOB baseaddr 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-27 10:21:38 +01:00
Tomasz Michalak 13ba74194a zynq: Add BRKH_INT_PSS tile type to fix assertion 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2020-01-27 10:20:22 +01:00
Alessandro Comodi 0b623982e5 divided harness and extra parts creation 
There is an issue with the roi_harness creation, for which the
multi-process make does not correctly works for roi_harness target

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 5ae155fd9c copy tileconn.json in the correct diretory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 117f3e51b2 revert 074 and 072 to use previous Makefile configuration 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 4a0ca41077 roi_only: copy tilegrid and tileconn from equivalent part 
005-tilegrid fuzzer cannot run for some parts as some of the IOBs are
not available, therefore the fuzzer exits with errors.

Instead, the tilegrid is copied from the specified equivalent part.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi dfb0717f2c fix makefile part_only dependencies 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 4849f49724 005-tilegrid: added comment on EXCLUDE_ROI env variable 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 5db213293c 072-ordered_wires: better handling of Lock 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 15d914f2c5 074-dump_all: changed ignored_wires location 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 90d88bc7a2 fix roi_only parts 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 88f7830456 addressed review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 9a88b77620 run make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e464172e03 074-dump_all: exclude tiles and node that are in the excluded roi 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi cb9944d392 005-tilegrid: use variable for dependencies 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 070931ec6e 074-dump_all: fix tilegrid location 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 61cd47dc36 043-clk-rebuf-pips: fixed missing argument 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 127412b5b9 fix wrong location of tilegrid and yaml 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e84a1d63df 075-pins: create destination directory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e44027bcaf Move all part-specific files to dedicated directory 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 3865c726f2 074-dump_all: increase jobs and tiles per job 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 63bb8337f8 072-ordered_wires: increased parallel jobs. 
This changes also the way the ordered wires final files are generated.
In fact, now, with the help of a Lock, all the suprocesses directly
access the final files, updating them. Once the write completes, the
temporary file is deleted.

This saves up disk space.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi c5a33cb161 005-tilegrid: further increasing to 6 number of specimens for mmcm 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi e8a2777a17 005-tilegrid: reduce number of specimens 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 5c829daa8c 005-tilegrid: fixed some over-specific settings in generate_full 
Also added specimens to make some rquired fuzzers find all necessary
features

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Alessandro Comodi 93d1ae82f7 Enable the generation of extra part-dependents files 
This change affects the extra-db target, by adding also the generation
of other part-dependent files, such as tilegrid, tileconn, and others.

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-01-24 10:13:33 +01:00
Keith Rothman cce638930c Add clock_region to tilegrid.json for constructing clock networks. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-12-14 22:28:22 -08:00
litghost cc9e00da8f
Merge pull request #1174 from antmicro/zynq_ps7_clocks 
Zynq PS7 clocks
 2019-12-12 13:05:29 -08:00
litghost 0d0a38cf52
Merge pull request #1175 from antmicro/zynq_ps7_ppips 
Dumping PPIPs for Zynq PS7
 2019-12-12 08:50:12 -08:00
Maciej Kurc 810473ef46 Disabled initialization of LIOB3/LIOI33 segbit files for Zynq7 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-12 17:20:53 +01:00
Maciej Kurc ef8d405bdb Added dumping of PPIPs for Zynq PS7 tiles and interconnects. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-12 09:57:41 +01:00
Maciej Kurc 0507f92345 Ran make format 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-12 09:31:59 +01:00
Maciej Kurc 24ccfb3bb5 Automatic inference of CLK_HROW with PS7 clocks, use of todo list for PS7 clock sources. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 22:39:04 +01:00
Maciej Kurc fb65464c42 A little hacky but working version. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 19:05:04 +01:00
Maciej Kurc d84c28b38c Modified fuzzer 075 to dump IO bank number for each pin. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 17:10:41 +01:00
Maciej Kurc 6086e6d6f5 Modified fuzzer 041 to solve Zynq PS7 FCLK clocks. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-11 16:25:45 +01:00
Maciej Kurc 7bd13efdcb WIP 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-10 15:21:28 +01:00
Maciej Kurc a4a033226f Modified fuzzer 001 to include required features for Zynq parts. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-12-10 14:38:24 +01:00
Alessandro Comodi 9401d1c730 071-ppips: fix wrong ppip in ioi tiles 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-12-05 16:40:33 +01:00
Tomasz Michalak 24070da931 001-part-yaml: Add iobanks information to part's json 
Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
 2019-12-02 21:39:32 +01:00
Maciej Kurc cc7ba29c6b Added forcing of manual routing through "BB" pips to toggle more bits. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-15 12:14:06 +01:00
Maciej Kurc 03b0b9cefc Added separate clock inputs for PLLs. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-15 12:13:49 +01:00
Maciej Kurc 6fd00834b2 Fixed bit names formatting. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-11-14 16:09:44 +01:00
Alessandro Comodi 99d31d2e67 071-ppips: skip HCLK_IOI_CK_IGCLK0 ppips addition 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-11-07 15:03:44 +01:00
litghost 4cec0817ab
Merge pull request #1080 from JakeMercer/dsp 
DSP - Add Attribute Fuzzing
 2019-11-04 08:16:53 -08:00
Alessandro Comodi 827081b3b5 hlck-ioi: fix empty list bug in generate.tcl 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-11-04 11:02:52 +01:00
Jake Mercer 6a3db24da1 FUZZER - DSP - Fixes Following Review 
Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 15cfb5bd46 FUZZER - DSP - Add Ports & ROI Module 
Added code for ports to the DSP48E1 instances.  Moved DSP instances
inside an ROI module and using the verilog top harness as in other
fuzzers.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer e0fb0c0cb1 FUZZER - DSP - Refactor 
Refactor the DSP Python scripts to be easier to manage.  Use JSON
instead of CSV.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 596bb27e3b FUZZER - DSP - Add All Attributes 
Added the rest of the DSP attributes; there are still some issues with mapping the bits.
AREG/BREG mode 2 will require inputs to be connected.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 8da263c502 FUZZER - DSP - Refactor for Readability & Extensibility 
Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 624de250e8 FUZZER - DSP - Cleared Bits 
Changed some tags to be prefixed with 'Z'; these bits are cleared and need the prefix to indicate
the inversion so that they are resolved to the DB correctly.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer 78d64f7558 FUZZER - DSP - Add AUTORESET_PATDET Attribute Fuzzing 
Added fuzzing for the AUTORESET_PATDET attribute of the DSP48 block.  Values are RESET_MATCH,
NO_RESET, and RESET_NOT_MATCH; so this can be represented by 2 bits.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Jake Mercer c575adf8a0 FUZZER - DSP - Add A & B Input Attributes 
Adding `A_INPUT` and `B_INPUT` attribute fuzzing for the DSP48 tiles.

Signed-off-by: Jake Mercer <jmercer04@qub.ac.uk>
 2019-11-02 11:43:12 +00:00
Alessandro Comodi 13361904ee hclk-ioi: make 047a dependent on 47 to avoid race condition on piplist 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 17:00:33 +01:00
Alessandro Comodi 949cf722d1 hclk-ioi: re-add IDELAYCTRL to exclude-RE 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 12:04:43 +01:00
Alessandro Comodi b057e35e73 hclk-ioi: addressed review comments 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 0cf48f337a hclk-ioi: re-added whole top.py file to avoid having const1 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 1ad84b2b44 hclk-ioi: reduce probability of using lut output as BUFR clock 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 2fb40d0232 hclk-ioi: moved IDELAYCTRL to new parallel fuzzer 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
Alessandro Comodi 127022c2a9 hclk-ioi: added IMUX to BEFORE_DIV pips 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-31 11:58:11 +01:00
litghost 78cf96be0f
Merge pull request #1122 from JakeMercer/whitespace 
Whitespace
 2019-10-29 15:04:39 -07:00
Maciej Kurc b99bd85fa4 Added handling of routing failure in the TCL script. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 18:20:50 +01:00
Maciej Kurc 0377b5fb4c Disabled reading PIPs and PPIPs for "R" version of CMT tiles for Zynq7. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 17:43:10 +01:00
Maciej Kurc 573ee1a38d Fixed bug in tag_groups.txt 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 11:55:03 +01:00
Maciej Kurc bf380f2bdd PIPs and PPIPs are now not read from the db. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-29 11:50:40 +01:00
Maciej Kurc 8267bcdaeb Updated regex for PIP todo list. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 5ab90a604d Inceased N 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 355a571400 Removed the INTERNAL_FEEDBACK tag as it is the same as the PLLE2.COMPENSATION.INTENAL 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 4a6930694f Reworked fuzzer, added README.md 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 73c8652858 Ran make format_py 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc 56258694aa Added rejection of conflicting features. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:59:38 +01:00
Maciej Kurc f88a1d54b8 Fixed makefile 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:58:58 +01:00
Maciej Kurc a4250c1487 Comments. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:58:58 +01:00
Maciej Kurc 205bc5c1df Code formatting. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:58:58 +01:00
Maciej Kurc 89abe7ad47 Modified 034 to manually force routing through specific PIPs and exclude PPIPs from segdata. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-28 15:57:22 +01:00
Jake Mercer c05b4b0406 MAKE - Format Trailing Whitespace 
Add `make format-trailing-ws`.  This recipe finds all _files_ (not
links) known to Git and uses `sed` to remove trailing whitespace.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-26 10:04:52 +01:00
litghost f1f86a02bf
Merge pull request #1118 from antmicro/more_ppips 
Dump PPIPs for additional clock related tiles.
 2019-10-25 08:06:36 -07:00
Alessandro Comodi 8914753211 run make format 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-24 17:45:04 +02:00
Maciej Kurc 7911d78a8f Removed dumping PPIPs for CLK_BUFG_REBUF. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-24 17:42:49 +02:00
Alessandro Comodi 04234ec75c 036-ologic: change OSERDESE prefix to OSERDES 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-24 17:34:31 +02:00
Alessandro Comodi 1d26c91d4a oserdese: fix wrong fasm prefix 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2019-10-24 15:56:18 +02:00
Maciej Kurc a88e73f65e Added dumping of PPIPs for additional clock routing related tiles. 
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
 2019-10-24 10:20:47 +02:00
Keith Rothman 97699e4e93 Add HCLK_[LR]_BOT_UTURN aliases. 
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-10-23 15:30:27 -07:00
litghost c94cb0224c
Revert "Whitespace" 2019-10-23 14:22:17 -07:00
Jake Mercer bf11f43390 FORMAT - Run `make format` 
Changes after running `make format`.  Future commits which add
whitespace should be caught by CI at the PR stage.

Signed-off-by: Jake Mercer <jake.mercer@civica.co.uk>
 2019-10-22 19:35:24 +01:00
Keith Rothman c0b8aef3a9 Add pin functions to tilegrid. 
- Add support to emit PUDC_B pullup if unused (for A7 and Z7 fabrics).

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
 2019-10-14 16:38:02 -07:00