mirror of https://github.com/openXC7/prjxray.git
bitstream writer utility class
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
02d28f2920
commit
fe49ac6cee
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@ -3,6 +3,7 @@ add_library(libprjxray
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memory_mapped_file.cc
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segbits_file_reader.cc
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xilinx/xc7series/bitstream_reader.cc
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xilinx/xc7series/bitstream_writer.cc
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xilinx/xc7series/block_type.cc
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xilinx/xc7series/configuration_bus.cc
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xilinx/xc7series/configuration_column.cc
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@ -41,6 +42,7 @@ if (PRJXRAY_BUILD_TESTING)
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add_executable(xilinx_xc7series_test
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xilinx/xc7series/bitstream_reader_test.cc
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xilinx/xc7series/bitstream_writer_test.cc
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xilinx/xc7series/block_type_test.cc
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xilinx/xc7series/frame_address_test.cc
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xilinx/xc7series/configuration_bus_test.cc
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@ -0,0 +1,113 @@
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/*
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* Takes in a collection of ConfigurationPacket and writes them to specified
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* file This includes the following: -Bus auto detection -Sync Word -FPGA
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* configuration
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*/
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#ifndef PRJXRAY_LIB_XILINX_XC7SERIES_BITSTREAM_WRITER_H
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#define PRJXRAY_LIB_XILINX_XC7SERIES_BITSTREAM_WRITER_H
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#include <algorithm>
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#include <memory>
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#include <vector>
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#include <absl/types/optional.h>
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#include <absl/types/span.h>
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#include <prjxray/big_endian_span.h>
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#include <prjxray/xilinx/xc7series/configuration_packet.h>
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namespace prjxray {
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namespace xilinx {
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namespace xc7series {
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class BitstreamWriter {
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public:
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typedef std::array<uint32_t, 6> header_t;
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typedef std::vector<ConfigurationPacket> packets_t;
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// Only defined if a packet exists
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typedef absl::optional<absl::Span<uint32_t>> op_data_t;
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typedef absl::Span<uint32_t>::iterator data_iterator_t;
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using itr_value_type = uint32_t;
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class packet_iterator
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: public std::iterator<std::input_iterator_tag, itr_value_type> {
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public:
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packet_iterator& operator++();
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bool operator==(const packet_iterator& other) const;
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bool operator!=(const packet_iterator& other) const;
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const itr_value_type operator*() const;
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const itr_value_type operator->() const;
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typedef enum {
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STATE_HEADER = 1,
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STATE_DATA = 2,
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STATE_END = 3,
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} state_t;
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protected:
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explicit packet_iterator(const ConfigurationPacket* packet,
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state_t state,
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data_iterator_t itr_data);
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private:
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friend iterator;
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friend BitstreamWriter;
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// Data iterators
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// First over the fixed header, then the configuration data
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state_t state_;
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// Over packet.data()
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data_iterator_t itr_data_;
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const ConfigurationPacket* packet_;
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};
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using value_type = uint32_t;
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class iterator
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: public std::iterator<std::input_iterator_tag, itr_value_type> {
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public:
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iterator& operator++();
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bool operator==(const iterator& other) const;
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bool operator!=(const iterator& other) const;
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const itr_value_type operator*() const;
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const itr_value_type operator->() const;
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packet_iterator packet_begin();
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packet_iterator packet_end();
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protected:
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explicit iterator(
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header_t::iterator itr_header,
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const packets_t& packets,
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packets_t::const_iterator itr_packets,
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absl::optional<packet_iterator> op_itr_packet);
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private:
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friend BitstreamWriter;
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// Data iterators
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// First over the fixed header, then the configuration data
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header_t::iterator itr_header_;
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const packets_t& packets_;
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packets_t::const_iterator itr_packets_;
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absl::optional<packet_iterator> op_itr_packet_;
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};
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BitstreamWriter(const packets_t& packets);
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iterator begin();
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iterator end();
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private:
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static header_t header_;
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const packets_t& packets_;
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};
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} // namespace xc7series
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} // namespace xilinx
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} // namespace prjxray
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#endif // PRJXRAY_LIB_XILINX_XC7SERIES_BITSTREAM_WRITER_H
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@ -0,0 +1,225 @@
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/*
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* TODO
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* -Finish type 1/2 support
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* -Review sample bitstream padding. What are they for?
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*/
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#include <prjxray/xilinx/xc7series/bitstream_writer.h>
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#include <prjxray/bit_ops.h>
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namespace prjxray {
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namespace xilinx {
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namespace xc7series {
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// Per UG470 pg 80: Bus Width Auto Detection
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std::array<uint32_t, 6> BitstreamWriter::header_{
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0xFFFFFFFF, 0x000000BB, 0x11220044, 0xFFFFFFFF, 0xFFFFFFFF, 0xAA995566};
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/**************************************************
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* BitstreamWriter::BitstreamWriter
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*************************************************/
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BitstreamWriter::BitstreamWriter(const packets_t& packets)
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: packets_(packets) {}
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/**************************************************
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*
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*************************************************/
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BitstreamWriter::packet_iterator BitstreamWriter::iterator::packet_begin() {
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// itr_packets = packets.begin();
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const ConfigurationPacket& packet = *itr_packets_;
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return BitstreamWriter::packet_iterator(
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&packet, BitstreamWriter::packet_iterator::STATE_HEADER,
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packet.data().begin());
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}
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BitstreamWriter::packet_iterator BitstreamWriter::iterator::packet_end() {
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const ConfigurationPacket& packet = *itr_packets_;
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return BitstreamWriter::packet_iterator(
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&packet, BitstreamWriter::packet_iterator::STATE_END,
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// Essentially ignored
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packet.data().end());
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}
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BitstreamWriter::packet_iterator::packet_iterator(
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const ConfigurationPacket* packet,
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state_t state,
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data_iterator_t itr_data)
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: state_(state), itr_data_(itr_data), packet_(packet) {}
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BitstreamWriter::packet_iterator& BitstreamWriter::packet_iterator::
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operator++() {
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if (state_ == STATE_HEADER) {
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itr_data_ = packet_->data().begin();
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if (itr_data_ == packet_->data().end()) {
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state_ = STATE_END;
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} else {
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state_ = STATE_DATA;
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}
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} else if (state_ == STATE_DATA) {
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/// Advance. data must be valid while not at end
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itr_data_++;
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// Reached this end of this packet?
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if (itr_data_ == packet_->data().end()) {
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state_ = STATE_END;
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}
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}
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return *this;
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}
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bool BitstreamWriter::packet_iterator::operator==(
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const packet_iterator& other) const {
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return state_ == other.state_ && itr_data_ == other.itr_data_;
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}
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bool BitstreamWriter::packet_iterator::operator!=(
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const packet_iterator& other) const {
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return !(*this == other);
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}
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uint32_t packet2header(const ConfigurationPacket& packet) {
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uint32_t ret = 0;
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ret = bit_field_set(ret, 31, 29, packet.header_type());
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switch (packet.header_type()) {
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case 0x0:
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// Bitstreams are 0 padded sometimes, essentially making
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// a type 0 frame Ignore the other fields for now
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break;
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case 0x1: {
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// Table 5-20: Type 1 Packet Header Format
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ret = bit_field_set(ret, 28, 27, packet.opcode());
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ret = bit_field_set(ret, 26, 13, packet.address());
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ret = bit_field_set(ret, 10, 0, packet.data().length());
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break;
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}
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case 0x2: {
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// Table 5-22: Type 2 Packet Header
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// Note address is from previous type 1 header
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ret = bit_field_set(ret, 28, 27, packet.opcode());
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ret = bit_field_set(ret, 26, 0, packet.data().length());
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break;
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}
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default:
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break;
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}
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return ret;
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}
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const BitstreamWriter::itr_value_type BitstreamWriter::packet_iterator::
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operator*() const {
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if (state_ == STATE_HEADER) {
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return packet2header(*packet_);
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} else if (state_ == STATE_DATA) {
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return *itr_data_;
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}
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return 0; // XXX: assert or something?
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}
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const BitstreamWriter::itr_value_type BitstreamWriter::packet_iterator::
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operator->() const {
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return *(*this);
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}
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/**************************************************
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* BitstreamWriter::iterator
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*************************************************/
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BitstreamWriter::iterator BitstreamWriter::begin() {
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packets_t::const_iterator itr_packets = packets_.begin();
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absl::optional<packet_iterator> op_packet_itr;
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// May have no packets
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if (itr_packets != packets_.end()) {
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// op_packet_itr = packet_begin();
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// FIXME: de-duplicate this
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const ConfigurationPacket& packet = *itr_packets;
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packet_iterator packet_itr =
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packet_iterator(&packet, packet_iterator::STATE_HEADER,
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packet.data().begin());
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op_packet_itr = packet_itr;
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}
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return iterator(header_.begin(), packets_, itr_packets, op_packet_itr);
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}
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BitstreamWriter::iterator BitstreamWriter::end() {
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return iterator(header_.end(), packets_, packets_.end(),
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absl::optional<packet_iterator>());
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}
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BitstreamWriter::iterator::iterator(header_t::iterator itr_header,
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const packets_t& packets,
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packets_t::const_iterator itr_packets,
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absl::optional<packet_iterator> itr_packet)
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: itr_header_(itr_header),
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packets_(packets),
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itr_packets_(itr_packets),
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op_itr_packet_(itr_packet) {}
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BitstreamWriter::iterator& BitstreamWriter::iterator::operator++() {
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// Still generating header?
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if (itr_header_ != header_.end()) {
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itr_header_++;
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// Finished header?
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// Will advance to initialized itr_packets value
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// XXX: maybe should just overwrite here
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if (itr_header_ == header_.end()) {
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itr_packets_ = packets_.begin();
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if (itr_packets_ != packets_.end()) {
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op_itr_packet_ = packet_begin();
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}
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}
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// Then somewhere in packets
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} else {
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// We are either at end() in which case this operation is
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// invalid Or there is a packet in progress packet in progress?
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// Advance it
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++(*op_itr_packet_);
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// Done with this packet?
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if (*op_itr_packet_ == packet_end()) {
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itr_packets_++;
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if (itr_packets_ == packets_.end()) {
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// we are at the very end
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// invalidate data to be neat
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op_itr_packet_.reset();
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} else {
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op_itr_packet_ = packet_begin();
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}
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}
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}
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return *this;
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}
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bool BitstreamWriter::iterator::operator==(const iterator& other) const {
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return itr_header_ == other.itr_header_ &&
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itr_packets_ == other.itr_packets_ &&
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op_itr_packet_ == other.op_itr_packet_;
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}
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bool BitstreamWriter::iterator::operator!=(const iterator& other) const {
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return !(*this == other);
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}
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const BitstreamWriter::itr_value_type BitstreamWriter::iterator::operator*()
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const {
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if (itr_header_ != header_.end()) {
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return *itr_header_;
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} else {
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// Iterating over packets, get data from current packet position
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return *(*op_itr_packet_);
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}
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}
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const BitstreamWriter::itr_value_type BitstreamWriter::iterator::operator->()
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const {
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return *(*this);
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}
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} // namespace xc7series
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} // namespace xilinx
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} // namespace prjxray
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@ -0,0 +1,190 @@
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#include <array>
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#include <gtest/gtest.h>
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#include <prjxray/xilinx/xc7series/bitstream_reader.h>
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#include <prjxray/xilinx/xc7series/bitstream_writer.h>
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#include <prjxray/xilinx/xc7series/configuration_packet.h>
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#include <prjxray/xilinx/xc7series/configuration_register.h>
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#include <prjxray/bit_ops.h>
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namespace xc7series = prjxray::xilinx::xc7series;
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constexpr uint32_t kType1NOP = prjxray::bit_field_set<uint32_t>(0, 31, 29, 0x1);
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constexpr uint32_t MakeType1(const int opcode,
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const int address,
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const int word_count) {
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return prjxray::bit_field_set<uint32_t>(
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prjxray::bit_field_set<uint32_t>(
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prjxray::bit_field_set<uint32_t>(
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prjxray::bit_field_set<uint32_t>(0x0, 31, 29, 0x1), 28, 27,
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opcode),
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26, 13, address),
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10, 0, word_count);
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}
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constexpr uint32_t MakeType2(const int opcode, const int word_count) {
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return prjxray::bit_field_set<uint32_t>(
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prjxray::bit_field_set<uint32_t>(
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prjxray::bit_field_set<uint32_t>(0x0, 31, 29, 0x2), 28, 27,
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opcode),
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26, 0, word_count);
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}
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void dump_packets(xc7series::BitstreamWriter writer, bool nl = true) {
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int i = 0;
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// for (uint32_t x : itr) {
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for (auto itr = writer.begin(); itr != writer.end(); ++itr) {
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if (nl) {
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printf("% 3d: 0x0%08X\n", i, *itr);
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} else {
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printf("0x0%08X, ", *itr);
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}
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fflush(stdout);
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++i;
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}
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if (!nl) {
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printf("\n");
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}
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}
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// Special all 0's
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void AddType0(std::vector<xc7series::ConfigurationPacket>& packets) {
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// InitWithWords doesn't like type 0
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/*
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static std::vector<uint32_t> words{0x00000000};
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absl::Span<uint32_t> word_span(words);
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auto packet = xc7series::ConfigurationPacket::InitWithWords(word_span);
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packets.push_back(*(packet.second));
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*/
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static std::vector<uint32_t> words{};
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absl::Span<uint32_t> word_span(words);
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// CRC is config value 0
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packets.push_back(xc7series::ConfigurationPacket(
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0, xc7series::ConfigurationPacket::NOP,
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xc7series::ConfigurationRegister::CRC, word_span));
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}
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void AddType1(std::vector<xc7series::ConfigurationPacket>& packets) {
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static std::vector<uint32_t> words{MakeType1(0x2, 0x3, 2), 0xAA, 0xBB};
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absl::Span<uint32_t> word_span(words);
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auto packet = xc7series::ConfigurationPacket::InitWithWords(word_span);
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packets.push_back(*(packet.second));
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}
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// Empty
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void AddType1E(std::vector<xc7series::ConfigurationPacket>& packets) {
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static std::vector<uint32_t> words{MakeType1(0x2, 0x3, 0)};
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absl::Span<uint32_t> word_span(words);
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auto packet = xc7series::ConfigurationPacket::InitWithWords(word_span);
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packets.push_back(*(packet.second));
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}
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void AddType2(std::vector<xc7series::ConfigurationPacket>& packets) {
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// Type 1 packet with address
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// Without this InitWithWords will fail on type 2
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xc7series::ConfigurationPacket* packet1;
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{
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static std::vector<uint32_t> words{MakeType1(0x2, 0x3, 0)};
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absl::Span<uint32_t> word_span(words);
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auto packet1_pair =
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xc7series::ConfigurationPacket::InitWithWords(word_span);
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packets.push_back(*(packet1_pair.second));
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packet1 = &packets[0];
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}
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// Type 2 packet with data
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{
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static std::vector<uint32_t> words{
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MakeType2(0x01, 12), 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12};
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absl::Span<uint32_t> word_span(words);
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auto packet = xc7series::ConfigurationPacket::InitWithWords(
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word_span, packet1);
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packets.push_back(*(packet.second));
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}
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}
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// Empty packets should produce just the header
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TEST(BitstreamWriterTest, WriteHeader) {
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std::vector<xc7series::ConfigurationPacket> packets;
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xc7series::BitstreamWriter writer(packets);
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std::vector<uint32_t> words(writer.begin(), writer.end());
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// Per UG470 pg 80: Bus Width Auto Detection
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||||
std::vector<uint32_t> ref_header{0xFFFFFFFF, 0x000000BB, 0x11220044,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0xAA995566};
|
||||
EXPECT_EQ(words, ref_header);
|
||||
|
||||
// dump_packets(writer);
|
||||
}
|
||||
|
||||
TEST(BitstreamWriterTest, WriteType0) {
|
||||
std::vector<xc7series::ConfigurationPacket> packets;
|
||||
AddType0(packets);
|
||||
xc7series::BitstreamWriter writer(packets);
|
||||
// dump_packets(writer, false);
|
||||
std::vector<uint32_t> words(writer.begin(), writer.end());
|
||||
std::vector<uint32_t> ref{// Bus width + sync
|
||||
0x0FFFFFFFF, 0x0000000BB, 0x011220044,
|
||||
0x0FFFFFFFF, 0x0FFFFFFFF, 0x0AA995566,
|
||||
// Type 0
|
||||
0x00000000};
|
||||
EXPECT_EQ(words, ref);
|
||||
}
|
||||
TEST(BitstreamWriterTest, WriteType1) {
|
||||
std::vector<xc7series::ConfigurationPacket> packets;
|
||||
AddType1(packets);
|
||||
xc7series::BitstreamWriter writer(packets);
|
||||
// dump_packets(writer, false);
|
||||
std::vector<uint32_t> words(writer.begin(), writer.end());
|
||||
std::vector<uint32_t> ref{// Bus width + sync
|
||||
0x0FFFFFFFF, 0x0000000BB, 0x011220044,
|
||||
0x0FFFFFFFF, 0x0FFFFFFFF, 0x0AA995566,
|
||||
// Type 1
|
||||
0x030006002, 0x0000000AA, 0x0000000BB};
|
||||
EXPECT_EQ(words, ref);
|
||||
}
|
||||
|
||||
TEST(BitstreamWriterTest, WriteType2) {
|
||||
std::vector<xc7series::ConfigurationPacket> packets;
|
||||
AddType2(packets);
|
||||
xc7series::BitstreamWriter writer(packets);
|
||||
// dump_packets(writer, false);
|
||||
std::vector<uint32_t> words(writer.begin(), writer.end());
|
||||
std::vector<uint32_t> ref{
|
||||
// Bus width + sync
|
||||
0x0FFFFFFFF, 0x0000000BB, 0x011220044, 0x0FFFFFFFF, 0x0FFFFFFFF,
|
||||
0x0AA995566,
|
||||
// Type 1 + type 2 header
|
||||
0x030006000, 0x04800000C, 0x000000001, 0x000000002, 0x000000003,
|
||||
0x000000004, 0x000000005, 0x000000006, 0x000000007, 0x000000008,
|
||||
0x000000009, 0x00000000A, 0x00000000B, 0x00000000C};
|
||||
EXPECT_EQ(words, ref);
|
||||
}
|
||||
|
||||
TEST(BitstreamWriterTest, WriteMulti) {
|
||||
std::vector<xc7series::ConfigurationPacket> packets;
|
||||
AddType1(packets);
|
||||
AddType1E(packets);
|
||||
AddType2(packets);
|
||||
AddType1E(packets);
|
||||
xc7series::BitstreamWriter writer(packets);
|
||||
// dump_packets(writer, false);
|
||||
std::vector<uint32_t> words(writer.begin(), writer.end());
|
||||
std::vector<uint32_t> ref{
|
||||
// Bus width + sync
|
||||
0x0FFFFFFFF, 0x0000000BB, 0x011220044, 0x0FFFFFFFF, 0x0FFFFFFFF,
|
||||
0x0AA995566,
|
||||
// Type1
|
||||
0x030006002, 0x0000000AA, 0x0000000BB,
|
||||
// Type1
|
||||
0x030006000,
|
||||
// Type 1 + type 2 header
|
||||
0x030006000, 0x04800000C, 0x000000001, 0x000000002, 0x000000003,
|
||||
0x000000004, 0x000000005, 0x000000006, 0x000000007, 0x000000008,
|
||||
0x000000009, 0x00000000A, 0x00000000B, 0x00000000C,
|
||||
// Type 1
|
||||
0x030006000};
|
||||
EXPECT_EQ(words, ref);
|
||||
}
|
||||
Loading…
Reference in New Issue