mirror of https://github.com/openXC7/prjxray.git
timfuz: utility to create tile to speed model database
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
5176374817
commit
fb69b9f045
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@ -0,0 +1,74 @@
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#!/usr/bin/env python3
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import sys
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import os
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import time
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import json
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SI_NONE = 0xFFFF
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def load_speed_json(f):
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j = json.load(f)
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# Index speed indexes to names
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speed_i2s = {}
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for k, v in j['speed_model'].items():
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i = v['speed_index']
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if i != SI_NONE:
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speed_i2s[i] = k
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return j, speed_i2s
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def gen_tiles(fnin, speed_i2s):
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for l in open(fnin):
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# lappend items pip $name $speed_index
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# puts $fp "$type $tile $grid_x $grid_y $items"
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parts = l.strip().split()
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tile_type, tile_name, grid_x, grid_y = parts[0:4]
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grid_x, grid_y = int(grid_x), int(grid_y)
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tuples = parts[4:]
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assert len(tuples) % 3 == 0
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pips = {}
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wires = {}
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for i in range(0, len(tuples), 3):
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ttype, name, speed_index = tuples[i:i+3]
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name_local = name.split('/')[1]
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{
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'pip': pips,
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'wire': wires,
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}[ttype][name_local] = speed_i2s[int(speed_index)]
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yield (tile_type, tile_name, grid_x, grid_y, pips, wires)
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def run(fnin, fnout, speed_json_fn, verbose=False):
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speedj, speed_i2s = load_speed_json(open(speed_json_fn, 'r'))
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tiles = {}
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for tile in gen_tiles(fnin, speed_i2s):
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(tile_type, tile_name, grid_x, grid_y, pips, wires) = tile
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this_dat = {'pips': pips, 'wires': wires}
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if tile_type not in tiles:
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tiles[tile_type] = this_dat
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else:
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if tiles[tile_type] != this_dat:
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print(tile_name, tile_type)
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print(this_dat)
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print(tiles[tile_type])
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assert 0
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j = {'tiles': tiles}
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json.dump(j, open(fnout, 'w'), sort_keys=True, indent=4, separators=(',', ': '))
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def main():
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import argparse
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parser = argparse.ArgumentParser(
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description=
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'Solve timing solution'
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)
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parser.add_argument('--speed-json', default='build_speed/speed.json',
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help='Provides speed index to name translation')
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parser.add_argument('fnin', default=None, help='input tcl output .txt')
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parser.add_argument('fnout', default=None, help='output .json')
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args = parser.parse_args()
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run(args.fnin, args.fnout, speed_json_fn=args.speed_json, verbose=False)
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if __name__ == '__main__':
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main()
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@ -0,0 +1,26 @@
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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cp specimen_001/tilegrid.json tilegrid.json
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pushdb:
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cp tilegrid.json ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)/tilegrid.json
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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run:
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$(MAKE) clean
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$(MAKE) database
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$(MAKE) pushdb
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touch run.ok
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ tilegrid.json run.ok
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.PHONY: database pushdb clean run
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@ -0,0 +1,16 @@
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#!/bin/bash -x
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source ${XRAY_GENHEADER}
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vivado -mode batch -source ../generate.tcl
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for x in design*.bit; do
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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for x in design_*.bits; do
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diff -u design.bits $x | grep '^[-+]bit' > ${x%.bits}.delta
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done
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python3 ../generate.py design_*.delta > tilegrid.json
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@ -0,0 +1,119 @@
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proc create_project {} {
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if 0 {
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set grid_min_x -1
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set grid_max_x -1
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set grid_min_y -1
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set grid_max_y -1
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} {
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set grid_min_x $::env(XRAY_ROI_GRID_X1)
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set grid_max_x $::env(XRAY_ROI_GRID_X2)
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set grid_min_y $::env(XRAY_ROI_GRID_Y1)
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set grid_max_y $::env(XRAY_ROI_GRID_Y2)
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}
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb]
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create_pblock roi
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_param tcl.collectionResultDisplayLimit 0
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */A6LUT]
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set selected_luts {}
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set lut_index 0
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# LOC one LUT (a "selected_lut") into each CLB segment configuration column (ie 50 per column)
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# Also, if GRID_MIN/MAX is not defined, automatically create it based on used CLBs
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# See caveat in README on automatic creation
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foreach lut $luts {
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set tile [get_tile -of_objects $lut]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x}
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if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x}
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if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y}
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if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y}
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# 50 per column => 50, 100, 150, etc
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if [regexp "Y(0|[0-9]*[05]0)/" $lut] {
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set cell [get_cells roi/is[$lut_index].lut]
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set_property LOC [get_sites -of_objects $lut] $cell
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set lut_index [expr $lut_index + 1]
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lappend selected_luts $lut
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}
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}
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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proc write_data {} {
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if 0 {
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set grid_min_x -1
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set grid_max_x -1
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set grid_min_y -1
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set grid_max_y -1
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} {
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set grid_min_x $::env(XRAY_ROI_GRID_X1)
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set grid_max_x $::env(XRAY_ROI_GRID_X2)
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set grid_min_y $::env(XRAY_ROI_GRID_Y1)
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set grid_max_y $::env(XRAY_ROI_GRID_Y2)
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}
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# Get all tiles in ROI, ie not just the selected LUTs
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set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"]
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# Write tiles.txt with site metadata
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set fp [open "tiles.txt" w]
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foreach tile $tiles {
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set type [get_property TYPE $tile]
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set grid_x [get_property GRID_POINT_X $tile]
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set grid_y [get_property GRID_POINT_Y $tile]
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set items {}
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set wires [get_wires -of_objects $tile]
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if [llength $wires] {
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foreach wire $wires {
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set name [get_property NAME $wire]
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set speed_index [get_property SPEED_INDEX $wire]
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lappend items wire $name $speed_index
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}
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}
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set pips [get_pips -of_objects $tile]
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if [llength $pips] {
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foreach pip $pips {
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set name [get_property NAME $pip]
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set speed_index [get_property SPEED_INDEX $pip]
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lappend items pip $name $speed_index
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}
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}
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puts $fp "$type $tile $grid_x $grid_y $items"
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}
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close $fp
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}
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create_project
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write_data
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@ -0,0 +1,49 @@
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//Need at least one LUT per frame base address we want
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`define N 100
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 6;
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localparam integer DOUT_N = `N;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [5:0] din, output [`N-1:0] dout);
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genvar i;
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generate
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for (i = 0; i < `N; i = i+1) begin:is
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LUT6 #(
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.INIT(64'h8000_0000_0000_0001 + (i << 16))
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O(dout[i])
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);
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end
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endgenerate
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endmodule
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@ -0,0 +1,62 @@
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`define N 100
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 8;
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localparam integer DOUT_N = `N;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [7:0] din, output [`N-1:0] dout);
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genvar i;
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generate
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for (i = 0; i < `N; i = i+1) begin:is
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(* KEEP, DONT_TOUCH *)
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RAMB36E1 #(.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000)) ram (
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.CLKARDCLK(din[0]),
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.CLKBWRCLK(din[1]),
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.ENARDEN(din[2]),
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.ENBWREN(din[3]),
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.REGCEAREGCE(din[4]),
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.REGCEB(din[5]),
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.RSTRAMARSTRAM(din[6]),
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.RSTRAMB(din[7]),
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.RSTREGARSTREG(din[0]),
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.RSTREGB(din[1]),
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.ADDRARDADDR(din[2]),
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.ADDRBWRADDR(din[3]),
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.DIADI(din[4]),
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.DIBDI(din[5]),
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.DIPADIP(din[6]),
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.DIPBDIP(din[7]),
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.WEA(din[0]),
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.WEBWE(din[1]),
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.DOADO(dout[0]),
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.DOBDO(),
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.DOPADOP(),
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.DOPBDOP());
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end
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endgenerate
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endmodule
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