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prjxray
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A little hacky but working version. 

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc 2019-12-11 19:05:04 +01:00
parent 6086e6d6f5
commit fb65464c42
2 changed files with 10 additions and 15 deletions
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2
fuzzers/041-clk-hrow-pips/output_cmt.tcl
View File

@ -3,7 +3,7 @@ set_property design_mode PinPlanning [current_fileset]
open_io_design -name io_1 open_io_design -name io_1
set fp [open "cmt_regions.csv" "w"] set fp [open "cmt_regions.csv" "w"]
foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE BUFR PS7} { foreach site_type {MMCME2_ADV PLLE2_ADV BUFHCE BUFR} {
foreach site [get_sites -filter "SITE_TYPE == $site_type"] { foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
puts $fp "$site,[get_property CLOCK_REGION $site]" puts $fp "$site,[get_property CLOCK_REGION $site]"
} }

23
fuzzers/041-clk-hrow-pips/top.py
View File

@ -460,11 +460,11 @@ module top();
print("") print("")
for wire in clocks: for wire in clocks:
cmt = site_to_cmt[site]
cmt_tile = [d["tile"] for d in pss_clocks if d["pin"] == wire][0] cmt_tile = [d["tile"] for d in pss_clocks if d["pin"] == wire][0]
cmt_loc = get_cmt_loc(cmt_tile) cmt_loc = get_cmt_loc(cmt_tile)
clock_sources.add_clock_source(wire, cmt, cmt_loc) # FIXME: HACK
clock_sources.add_clock_source(wire, "X0Y0", cmt_loc)
print(" wire {};".format(wire)) print(" wire {};".format(wire))
print(""" print("""
@ -480,8 +480,6 @@ module top();
fclk3=clocks[3] fclk3=clocks[3]
)) ))
used_pss_clocks = set()
luts = LutMaker() luts = LutMaker()
bufhs = StringIO() bufhs = StringIO()
bufgs = StringIO() bufgs = StringIO()
@ -552,11 +550,10 @@ module top();
if random.random() > .05: if random.random() > .05:
wire_name = clock_sources.get_random_source(site_to_cmt[site]) wire_name = clock_sources.get_random_source(site_to_cmt[site])
# FIXME: HACK
if wire_name is not None and wire_name.startswith("PSS"): if wire_name is not None and wire_name.startswith("PSS"):
if wire_name not in used_pss_clocks: if "BOT" not in tile_name:
used_pss_clocks.add(wire_name) continue
else:
wire_name = None
if wire_name is None: if wire_name is None:
continue continue
@ -608,9 +605,8 @@ module top();
if random.randint(0, 1): if random.randint(0, 1):
wire_name = clock_sources.get_bufg_source( wire_name = clock_sources.get_bufg_source(
loc, tile_type, site, todos, 1, used_only) loc, tile_type, site, todos, 1, used_only)
if wire_name is not None and wire_name not in used_pss_clocks:
if wire_name.startswith("PSS"): if wire_name is not None:
used_pss_clocks.add(wire_name)
print( print(
""" """
assign I1_{site} = {wire_name};""".format( assign I1_{site} = {wire_name};""".format(
@ -621,9 +617,8 @@ module top();
if random.randint(0, 1): if random.randint(0, 1):
wire_name = clock_sources.get_bufg_source( wire_name = clock_sources.get_bufg_source(
loc, tile_type, site, todos, 0, used_only) loc, tile_type, site, todos, 0, used_only)
if wire_name is not None and wire_name not in used_pss_clocks:
if wire_name.startswith("PSS"): if wire_name is not None:
used_pss_clocks.add(wire_name)
print( print(
""" """
assign I0_{site} = {wire_name};""".format( assign I0_{site} = {wire_name};""".format(