mirror of https://github.com/openXC7/prjxray.git
Merge pull request #1705 from antmicro/fix-iob-ppips
071-ppips: add LIOB33 and RIOB33 ppips
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commit
f7f06896ad
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@ -27,7 +27,7 @@ route_design
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write_checkpoint -force design.dcp
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write_checkpoint -force design.dcp
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# write_bitstream -force design.bit
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# write_bitstream -force design.bit
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proc write_clb_ppips_db {filename tile} {
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proc write_common_ppips_db {filename tile} {
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set fp [open $filename "w"]
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set fp [open $filename "w"]
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set tile [get_tiles $tile]
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set tile [get_tiles $tile]
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set tile_type [get_property TILE_TYPE $tile]
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set tile_type [get_property TILE_TYPE $tile]
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@ -292,7 +292,7 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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set tile [lindex $tiles 0]
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write_clb_ppips_db "ppips_[string tolower $tile_type].db" $tile
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write_common_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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}
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}
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@ -391,3 +391,11 @@ foreach tile_type {PCIE_INT_INTERFACE_L PCIE_INT_INTERFACE_R} {
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write_pcie_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile $allow_wires $forbid_wires
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write_pcie_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile $allow_wires $forbid_wires
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}
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}
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}
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}
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foreach tile_type {RIOB33 LIOB33 RIOB33_SING LIOB33_SING} {
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set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
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if {[llength $tiles] != 0} {
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set tile [lindex $tiles 0]
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write_common_ppips_db "ppips_[string tolower $tile_type].db" $tile
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}
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}
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