mirror of https://github.com/openXC7/prjxray.git
Enhance 045 to solve FREQ_REF related PIPs
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
This commit is contained in:
Maciej Kurc
parent
1f23cb2d35
commit
f6dd2c1e7c
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@ -3,57 +3,44 @@ PIP_TYPE?=hclk_cmt
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PIPLIST_TCL=$(FUZDIR)/hclk_cmt_pip_list.tcl
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TODO_RE=".*"
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# Skipped pips:
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# - FREQ_REF is only used by interconnect clocks, so low likelyhood of usage.
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# A BUFR can be used to clock divide if needed
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# - PHSR PIPs are connected to PHASER sites, which are undocumented, so avoid
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# for now.
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EXCLUDE_RE="(^.*LEAF)|(^.*BUFMR)|(^.*FREQ_REF)|(^.*PHSR)|(^.*CLK_PLL7)|(^.*CLK_MMCM13)"
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EXCLUDE_RE="(^.*LEAF)|(^.*BUFMR)|(^.*PHSR)|(^.*CLK_PLL7)|(^.*CLK_MMCM13)"
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MAKETODO_FLAGS=--sides ",l" --pip-type ${PIP_TYPE} --seg-type ${PIP_TYPE} --re $(TODO_RE) --exclude-re $(EXCLUDE_RE)
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N = 100
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# These PIPs all appear to be either a 1 bit solutions.
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SEGMATCH_FLAGS=-c 2
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# All PIPs seem to have 2 bits. An exception is FREQ_REF which cannot be
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# decoupled from the others, hence it will always have 4 bits.
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FOUR_BIT_PIPS="FREQ_REF"
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SPECIMENS_DEPS=build/cmt_regions.csv
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A_PIPLIST=hclk_cmt.txt
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include ../pip_loop.mk
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build/segbits_hclk_cmt.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_hclk_cmt.rdb \
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$(shell find build -name segdata_hclk_cmt.txt)
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.PRECIOUS: build/%.rdb
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build/segbits_hclk_cmt.db: build/segbits_hclk_cmt.rdb
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build/%.rdb: $(SPECIMENS_OK)
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$(XRAY_SEGMATCH) -c 4 -o $@.4 $(shell find build -name $(subst segbits,segdata,$(patsubst %.rdb,%.txt,$(notdir $@))))
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$(XRAY_SEGMATCH) -c 2 -o $@.2 $(shell find build -name $(subst segbits,segdata,$(patsubst %.rdb,%.txt,$(notdir $@))))
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grep ${FOUR_BIT_PIPS} $@.4 > $@
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grep -v ${FOUR_BIT_PIPS} $@.2 >> $@
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build/%.db: build/%.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_hclk_cmt.rdb \
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--seg-fn-out build/segbits_hclk_cmt.db
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--seg-fn-in $< \
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--seg-fn-out $@
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# Keep a copy to track iter progress
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cp build/segbits_hclk_cmt.rdb build/$(ITER)/segbits_hclk_cmt.rdb
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${XRAY_MASKMERGE} build/mask_hclk_cmt.db \
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$(shell find build -name segdata_hclk_cmt.txt)
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build/segbits_hclk_cmt_l.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} ${SEGMATCH_FLAGS} -o build/segbits_hclk_cmt_l.rdb \
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$(shell find build -name segdata_hclk_cmt_l.txt)
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build/segbits_hclk_cmt_l.db: build/segbits_hclk_cmt_l.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
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--seg-fn-in build/segbits_hclk_cmt_l.rdb \
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--seg-fn-out build/segbits_hclk_cmt_l.db
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# Keep a copy to track iter progress
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cp build/segbits_hclk_cmt_l.rdb build/$(ITER)/segbits_hclk_cmt_l.rdb
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${XRAY_MASKMERGE} build/mask_hclk_cmt_l.db \
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$(shell find build -name segdata_hclk_cmt_l.txt)
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cp $< build/$(ITER)/$(notdir $<)
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${XRAY_MASKMERGE} $(subst segbits,mask,$@) \
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$(shell find build -name $(subst segbits,segdata,$(patsubst %.db,%.txt,$(notdir $@))))
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database: build/segbits_hclk_cmt.db build/segbits_hclk_cmt_l.db
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# Clobber existing .db to eliminate potential conflicts
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
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cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits_hclk_cmt*.db build/database/${XRAY_DATABASE}
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} hclk_cmt build/segbits_hclk_cmt.db
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XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} hclk_cmt_l build/segbits_hclk_cmt_l.db
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@ -62,9 +49,9 @@ build/cmt_regions.csv: output_cmt.tcl
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cd build/ && ${XRAY_VIVADO} -mode batch -source ${FUZDIR}/output_cmt.tcl
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pushdb: database
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${XRAY_MERGEDB} hclk_cmt build/segbits_hclk_cmt.db
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${XRAY_MERGEDB} hclk_cmt build/database/${XRAY_DATABASE}/segbits_hclk_cmt.db
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${XRAY_MERGEDB} mask_hclk_cmt build/mask_hclk_cmt.db
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${XRAY_MERGEDB} hclk_cmt_l build/segbits_hclk_cmt_l.db
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${XRAY_MERGEDB} hclk_cmt_l build/database/${XRAY_DATABASE}/segbits_hclk_cmt_l.db
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${XRAY_MERGEDB} mask_hclk_cmt_l build/mask_hclk_cmt_l.db
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.PHONY: database pushdb
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@ -120,6 +120,11 @@ def main():
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segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
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for port in tile_ports[tile_type]:
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# These ones do not have any outgoing connections from the tile.
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if "FREQ_REF" in port:
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continue
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if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
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segmk.add_tile_tag(tile, "{}_USED".format(port), 1)
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else:
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@ -197,6 +197,47 @@ proc route_todo {} {
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}
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}
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proc make_manual_routes {filename} {
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puts "MANROUTE: Loading routes from $filename"
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set fp [open $filename r]
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foreach line [split [read $fp] "\n"] {
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if {$line eq ""} {
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continue
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}
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puts "MANROUTE: Line: $line"
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# Parse the line
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set fields [split $line " "]
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set net_name [lindex $fields 0]
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set wire_name [lindex $fields 1]
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# Check if that net exist
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if {[get_nets $net_name] eq ""} {
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puts "MANROUTE: net $net_name does not exist"
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continue
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}
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# Ripup it
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route_design -unroute -nets [get_nets $net_name]
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# Make the route
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set status [route_via $net_name [list $wire_name] 0]
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# Failure, skip manual routing of this net
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if { $status != 1 } {
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puts "MANROUTE: Manual routing failed!"
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set net [get_nets $net_name]
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set_property -quiet FIXED_ROUTE "" $net
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set_property IS_ROUTE_FIXED 0 $net
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continue
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}
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puts "MANROUTE: Success!"
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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@ -220,10 +261,11 @@ proc run {} {
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets]
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place_design
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route_design
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place_design -directive Quick
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route_design -directive Quick
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route_todo
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route_design
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make_manual_routes routes.txt
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route_design -directive Quick -preserve
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -2,6 +2,7 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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import re
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from prjxray import util
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from prjxray.lut_maker import LutMaker
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from prjxray.db import Database
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@ -15,8 +16,45 @@ def read_site_to_cmt():
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with open(os.path.join(os.getenv('FUZDIR'), 'build',
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'cmt_regions.csv')) as f:
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for l in f:
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site, cmt, _ = l.strip().split(',')
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yield (site, cmt)
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site, cmt, tile = l.strip().split(',')
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yield (tile, site, cmt)
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def make_ccio_route_options():
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# Read the PIP lists
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piplist_path = os.path.join(os.getenv("FUZDIR"), "..", "piplist", "build", "hclk_cmt")
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pips = []
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for fname in os.listdir(piplist_path):
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if not fname.endswith(".txt"):
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continue
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fullname = os.path.join(piplist_path, fname)
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with open(fullname, "r") as fp:
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pips += [l.strip() for l in fp.readlines()]
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# Get PIPs that mention FREQ_REFn wires. These are the ones that we want
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# force routing through.
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pips = [p for p in pips if "FREQ_REF" in p]
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# Sort by tile type
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options = {}
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for pip in pips:
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tile, dst, src = pip.split(".")
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for a, b in ((src, dst), (dst, src)):
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match = re.match(r".*FREQ_REF([0-3]).*", a)
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if match is not None:
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n = int(match.group(1))
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if tile not in options:
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options[tile] = {}
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if n not in options[tile]:
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options[tile][n] = set()
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options[tile][n].add(b)
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return options
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class ClockSources(object):
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@ -121,6 +159,14 @@ def get_paired_iobs(db, grid, tile_name):
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idx += 1
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# A map of y deltas to CCIO wire indices
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CCIO_INDEX = {
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-1: 0,
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-3: 1,
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+2: 3,
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+4: 2
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}
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# Move from HCLK_IOI column to IOB column
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idx += 1
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@ -134,7 +180,7 @@ def get_paired_iobs(db, grid, tile_name):
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for site, site_type in gridinfo.sites.items():
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if site_type in ['IOB33M', 'IOB18M']:
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yield tile_name, site, site_type[-3:-1]
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yield tile_name, site, site_type[-3:-1], CCIO_INDEX[dy]
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def check_allowed(mmcm_pll_dir, cmt):
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@ -176,7 +222,12 @@ def main():
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clock_sources = ClockSources()
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adv_clock_sources = ClockSources()
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site_to_cmt = dict(read_site_to_cmt())
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tile_site_cmt = list(read_site_to_cmt())
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site_to_cmt = {tsc[1] : tsc[2] for tsc in tile_site_cmt}
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cmt_to_hclk = {tsc[2] : tsc[0] for tsc in tile_site_cmt if tsc[0].startswith("HCLK_CMT_")}
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ccio_route_options = make_ccio_route_options()
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db = Database(util.get_db_root(), util.get_part())
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grid = db.grid()
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@ -208,11 +259,13 @@ def main():
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have_iob_clocks = random.random() > .1
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iob_to_hclk = {}
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iob_clks = {}
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for tile_name in sorted(hclk_cmt_tiles):
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for _, site, volt in get_paired_iobs(db, grid, tile_name):
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for _, site, volt, ccio in get_paired_iobs(db, grid, tile_name):
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iob_clock = 'clock_IBUF_{site}'.format(site=site)
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iob_to_hclk[site] = (tile_name, ccio)
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cmt = site_to_cmt[site]
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if cmt not in iob_clks:
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@ -374,7 +427,7 @@ module top({inputs});
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wire_name = clock_sources.get_random_source(
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site_to_cmt[site],
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uses_left_right_routing=True,
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no_repeats=mmcm_pll_only)
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no_repeats=mmcm_pll_only or have_iob_clocks)
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if wire_name is not None and 'BUFHCE' in wire_name:
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# Looping a BUFHCE to a BUFHCE requires using a hclk in the
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@ -415,10 +468,32 @@ module top({inputs});
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.O(O_{site})
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);""".format(I=random.choice(iob_clks[site_to_cmt[site]]), site=site))
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route_file = open("routes.txt", "w")
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def fix_ccio_route(net):
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# Get the IOB site name
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match = re.match(r".*_IBUF_(.*)", net)
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assert match is not None, net
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iob_site = match.group(1)
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# Get associated HCLK_CMT tile and CCIO wire index
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hclk_tile_name, ccio = iob_to_hclk[iob_site]
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# Get HCLK_CMT tile type
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hclk_tile = hclk_tile_name.rsplit("_", maxsplit=1)[0]
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# Pick a random route option
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opts = list(ccio_route_options[hclk_tile][ccio])
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route = random.choice(opts)
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route = "{}/{}".format(hclk_tile_name, route)
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route_file.write("{} {}\n".format(net, route))
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for _, site in gen_sites('PLLE2_ADV'):
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for cin in ('cin1', 'cin2', 'clkfbin'):
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if random.random() > .2:
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src = adv_clock_sources.get_random_source(site_to_cmt[site])
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src = adv_clock_sources.get_random_source(site_to_cmt[site], no_repeats=have_iob_clocks)
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src_cmt = adv_clock_sources.source_to_cmt[src]
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@ -430,6 +505,9 @@ module top({inputs});
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if src is None:
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continue
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if "IBUF" in src:
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fix_ccio_route(src)
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print(
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"""
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assign {cin}_{site} = {csrc};
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@ -438,7 +516,7 @@ module top({inputs});
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for _, site in gen_sites('MMCME2_ADV'):
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for cin in ('cin1', 'cin2', 'clkfbin'):
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if random.random() > .2:
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src = adv_clock_sources.get_random_source(site_to_cmt[site])
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src = adv_clock_sources.get_random_source(site_to_cmt[site], no_repeats=have_iob_clocks)
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src_cmt = adv_clock_sources.source_to_cmt[src]
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if 'IBUF' not in src and 'BUFR' not in src:
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@ -449,6 +527,9 @@ module top({inputs});
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if src is None:
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continue
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if "IBUF" in src:
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fix_ccio_route(src)
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print(
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"""
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assign {cin}_{site} = {csrc};
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