mirror of https://github.com/openXC7/prjxray.git
ffcfg minitest
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
04f37f2704
commit
f19e57b97b
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@ -0,0 +1,25 @@
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N := 3
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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all:
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bash runme.sh
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database: $(SPECIMENS_OK)
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../../tools/segmatch -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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bash ../../utils/mergedb.sh clbll_l seg_clblx.segbits
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bash ../../utils/mergedb.sh clbll_r seg_clblx.segbits
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bash ../../utils/mergedb.sh clblm_l seg_clblx.segbits
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bash ../../utils/mergedb.sh clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
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.PHONY: database pushdb clean
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@ -0,0 +1,5 @@
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#!/bin/bash
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set -ex
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vivado -mode batch -source runme.tcl
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../../tools/bitread -F $XRAY_ROI_FRAMES -o design.bits -zy design.bit
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python3 ../../utils/segprint.py design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103
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@ -0,0 +1,26 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,288 @@
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//https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/7series_scm.pdf
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//Places one of every FF primitive
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = 80;
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localparam integer DOUT_N = 20;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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module roi(input clk, input [79:0] din, output [19:0] dout);
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/*
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clbs = (
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'FD',
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'FD_1',
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'FDC',
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'FDC_1',
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'FDCE',
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'FDCE_1',
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'FDE',
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'FDE_1',
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'FDP',
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'FDP_1',
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'FDPE',
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'FDPE_1',
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'FDR',
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'FDR_1',
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'FDRE',
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'FDRE_1',
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'FDS',
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'FDS_1',
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'FDSE',
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'FDSE_1',
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)
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for i, clb in enumerate(clbs):
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print 'clb_%s clb_%s (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d ]));' % (clb, clb, i * 4, i * 1)
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*/
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clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
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clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
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clb_FDC clb_FDC (.clk(clk), .din(din[ 8 +: 4]), .dout(dout[ 2]));
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clb_FDC_1 clb_FDC_1 (.clk(clk), .din(din[ 12 +: 4]), .dout(dout[ 3]));
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clb_FDCE clb_FDCE (.clk(clk), .din(din[ 16 +: 4]), .dout(dout[ 4]));
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clb_FDCE_1 clb_FDCE_1 (.clk(clk), .din(din[ 20 +: 4]), .dout(dout[ 5]));
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clb_FDE clb_FDE (.clk(clk), .din(din[ 24 +: 4]), .dout(dout[ 6]));
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clb_FDE_1 clb_FDE_1 (.clk(clk), .din(din[ 28 +: 4]), .dout(dout[ 7]));
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clb_FDP clb_FDP (.clk(clk), .din(din[ 32 +: 4]), .dout(dout[ 8]));
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clb_FDP_1 clb_FDP_1 (.clk(clk), .din(din[ 36 +: 4]), .dout(dout[ 9]));
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clb_FDPE clb_FDPE (.clk(clk), .din(din[ 40 +: 4]), .dout(dout[ 10]));
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clb_FDPE_1 clb_FDPE_1 (.clk(clk), .din(din[ 44 +: 4]), .dout(dout[ 11]));
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clb_FDR clb_FDR (.clk(clk), .din(din[ 48 +: 4]), .dout(dout[ 12]));
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clb_FDR_1 clb_FDR_1 (.clk(clk), .din(din[ 52 +: 4]), .dout(dout[ 13]));
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clb_FDRE clb_FDRE (.clk(clk), .din(din[ 56 +: 4]), .dout(dout[ 14]));
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clb_FDRE_1 clb_FDRE_1 (.clk(clk), .din(din[ 60 +: 4]), .dout(dout[ 15]));
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clb_FDS clb_FDS (.clk(clk), .din(din[ 64 +: 4]), .dout(dout[ 16]));
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clb_FDS_1 clb_FDS_1 (.clk(clk), .din(din[ 68 +: 4]), .dout(dout[ 17]));
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clb_FDSE clb_FDSE (.clk(clk), .din(din[ 72 +: 4]), .dout(dout[ 18]));
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clb_FDSE_1 clb_FDSE_1 (.clk(clk), .din(din[ 76 +: 4]), .dout(dout[ 19]));
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endmodule
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// ---------------------------------------------------------------------
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module clb_FD (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y100", BEL="AFF" *)
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FD ff (
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.C(clk),
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.Q(dout),
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.D(din[0])
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);
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endmodule
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module clb_FD_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y101", BEL="AFF" *)
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FD_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0])
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);
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endmodule
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module clb_FDC (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y102", BEL="AFF" *)
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FDC ff (
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.C(clk),
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.Q(dout),
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.CLR(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDC_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y103", BEL="AFF" *)
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FDC_1 ff (
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.C(clk),
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.Q(dout),
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.CLR(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDCE (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y104", BEL="AFF" *)
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FDCE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDCE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y105", BEL="AFF" *)
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FDCE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.CLR(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDE (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y106", BEL="AFF" *)
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FDE ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.CE(din[1])
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);
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endmodule
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module clb_FDE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y107", BEL="AFF" *)
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FDE_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.CE(din[1])
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);
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endmodule
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module clb_FDP (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y108", BEL="AFF" *)
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FDP ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_FDP_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y109", BEL="AFF" *)
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FDP_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.PRE(din[1])
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);
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endmodule
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module clb_FDPE (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y110", BEL="AFF" *)
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FDPE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.PRE(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDPE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y111", BEL="AFF" *)
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FDPE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.PRE(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDR (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y112", BEL="AFF" *)
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FDR ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.R(din[1])
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);
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endmodule
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module clb_FDR_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y113", BEL="AFF" *)
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FDR_1 ff (
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.C(clk),
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.Q(dout),
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.D(din[0]),
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.R(din[1])
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);
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endmodule
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module clb_FDRE (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y114", BEL="AFF" *)
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FDRE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.R(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDRE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y115", BEL="AFF" *)
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FDRE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.R(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDS (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y116", BEL="AFF" *)
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FDS ff (
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.C(clk),
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.Q(dout),
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.S(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDS_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y117", BEL="AFF" *)
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FDS_1 ff (
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.C(clk),
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.Q(dout),
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.S(din[0]),
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.D(din[1])
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);
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endmodule
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module clb_FDSE (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y118", BEL="AFF" *)
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FDSE ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.S(din[1]),
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.D(din[2])
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);
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endmodule
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module clb_FDSE_1 (input clk, input [3:0] din, output dout);
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(* LOC="SLICE_X16Y119", BEL="AFF" *)
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FDSE_1 ff (
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.C(clk),
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.Q(dout),
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.CE(din[0]),
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.S(din[1]),
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.D(din[2])
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);
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endmodule
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