Merge pull request #1564 from antmicro/add-litepcie-minitest

Add litepcie minitest

Makefile

@@ -200,6 +200,8 @@ db-extras-artix7-parts: $(addprefix db-part-only-,$(ARTIX_PARTS))
 db-extras-artix7-harness:
 	+source settings/artix7.sh && \
 		XRAY_PART=xc7a100tcsg324-1 $(MAKE) -C fuzzers roi_only
+	+source settings/artix7.sh && \
+		XRAY_PART=xc7a100tfgg484-2 $(MAKE) -C fuzzers roi_only
 	+source settings/artix7_50t.sh && \
 		XRAY_PART=xc7a35tftg256-1 $(MAKE) -C fuzzers roi_only
 	+source settings/artix7_200t.sh && \

database/artix7/mapping/parts.yaml

@@ -11,6 +11,10 @@
   device: "xc7a100t"
   package: "fgg676"
   speedgrade: "1"
+"xc7a100tfgg484-2":
+  device: "xc7a100t"
+  package: "fgg484"
+  speedgrade: "2"
 "xc7a100tcsg324-1":
   device: "xc7a100t"
   package: "csg324"

minitests/hamsternz-displayport/.gitignore

@@ -0,0 +1,5 @@
+# Outputs
+display_port*
+
+# Build dirs
+build*

minitests/litex/litepcie/.gitignore

@@ -0,0 +1,7 @@
+# Build data
+build
+*.fasm
+*.ok
+
+# Riscv toolchain
+riscv*

minitests/litex/litepcie/Makefile

@@ -0,0 +1,48 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+SHELL = bash
+
+PART = xc7a100tfgg484-2
+PROJECT_NAME = pcie
+RISCV_DIR = riscv64-unknown-elf-gcc-8.1.0-2019.01.0-x86_64-linux-ubuntu14
+
+all: $(PROJECT_NAME).fasm
+
+clean:
+	@rm -rf build
+	@rm -f *.fasm
+
+clean_litex:
+	@rm -rf ${VIRTUAL_ENV}/src
+	@rm -f litex-install.ok
+
+clean_riscv:
+	@rm -rf $(RISCV_DIR)
+	@rm -f riscv-gcc.ok
+
+help:
+	@echo "Usage: make all"
+
+.PHONY: clean help
+
+litex-install.ok:
+	pip install -r requirements.txt
+	touch litex-install.ok
+
+riscv-gcc.ok:
+	wget -qO- https://static.dev.sifive.com/dev-tools/$(RISCV_DIR).tar.gz | tar -xz
+	touch riscv-gcc.ok
+
+build/netv2/gateware/netv2.bit: litex-install.ok riscv-gcc.ok
+	export PATH=${PATH}:${PWD}/${RISCV_DIR}/bin && \
+		source ${XRAY_VIVADO_SETTINGS} && \
+		${VIRTUAL_ENV}/src/litex-boards/litex_boards/targets/netv2.py --with-pcie --variant a7-100 --build
+
+$(PROJECT_NAME).fasm: build/netv2/gateware/netv2.bit
+	source $(XRAY_DIR)/settings/artix7.sh && env XRAY_PART=$(PART) ${XRAY_BIT2FASM} --verbose build/netv2/gateware/netv2.bit > $(PROJECT_NAME).fasm

minitests/litex/litepcie/README.md

@@ -0,0 +1,27 @@
+LitePCIe minitest
+=================
+
+This minitest is intended to provide a counter-prove on the possible remaining features to document for
+the Gigabit Transcievers (GTP tiles) and the PCIE\_2\_1 primitive.
+
+It uses the following litex modules:
+
+| Repo URL                                                  | SHA     |
+| --------------------------------------------------------- | ------- |
+| <https://github.com/enjoy-digital/litex>                  | 7abfbd9 |
+| <https://github.com/enjoy-digital/litedram>               | ab2423e |
+| <https://github.com/enjoy-digital/liteeth>                | 7448170 |
+| <https://github.com/enjoy-digital/liteiclink>             | 0980a7c |
+| <https://github.com/enjoy-digital/litepcie>               | 1d7b584 |
+| <https://github.com/enjoy-digital/litex-boards>           | 1d8f0a9 |
+| <https://github.com/m-labs/migen>                         | 40b1092 |
+| <https://github.com/nmigen/nmigen>                        | 490fca5 |
+| <https://github.com/litex-hub/pythondata-cpu-vexriscv>    | 16c5dde |
+
+The final FASM file with the `unknown bits` can be obtained by running the following:
+
+```bash
+make all
+```
+
+All the pre-requisites (LiteX, RISC-V toolchain, etc.) are automatically installed/built. It is required though to have Vivado installed in the system.

minitests/litex/litepcie/requirements.txt

@@ -0,0 +1,14 @@
+# Litex
+-e git+https://github.com/enjoy-digital/litex@7abfbd9825188d1f6d97453838e18ed7af5526a7#egg=litex
+-e git+https://github.com/enjoy-digital/litedram@ab2423e3dd06783d80fef7aeb43b7c5513c1f2f0#egg=litedram
+-e git+https://github.com/enjoy-digital/liteeth@7448170390ddf4b7c353ae10932377255581c25a#egg=liteeth
+-e git+https://github.com/enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91#egg=liteiclink
+-e git+https://github.com/enjoy-digital/litepcie@01d7b584e8c222ba986b4c8f939d690b9c6f6f7c#egg=litepcie
+-e git+https://github.com/litex-hub/litex-boards@1d8f0a98298e0ed9d5fed08daa7c25aded7ecbb4#egg=litex_boards
+
+# Migen and nMigen
+-e git+https://github.com/m-labs/migen@40b1092a05ec7659c42c8087b0c229dcfb5d9ca1#egg=migen
+-e git+https://github.com/nmigen/nmigen@490fca57457b16421f7b3f2c7812bb229b17744a#egg=nmigen
+
+
+-e git+https://github.com/litex-hub/pythondata-cpu-vexriscv@16c5dded21ca50b73a2bdafab10eeef2ca816818#egg=pythondata_cpu_vexriscv

minitests/litex/nexys_video_sata/.gitignore

@@ -1,7 +1,7 @@
-# Python data
-src
-
 # Build data
 build*
 sata.*
 *.ok
+
+# Riscv toolchain
+riscv*

minitests/litex/nexys_video_sata/README.md

@@ -8,12 +8,12 @@ It uses the following litex modules:
 
 | Repo URL                                                  | SHA     |
 | --------------------------------------------------------- | ------- |
-| <https://github.com/enjoy-digital/litex>                  | 8cfe3b6 |
+| <https://github.com/enjoy-digital/litex>                  | 7abfbd9 |
 | <https://github.com/enjoy-digital/litedram>               | ab2423e |
 | <https://github.com/enjoy-digital/liteeth>                | 7448170 |
 | <https://github.com/enjoy-digital/liteiclink>             | 0980a7c |
 | <https://github.com/enjoy-digital/litesata>               | fae9f8d |
-| <https://github.com/enjoy-digital/litex-boards>           | bee71da |
+| <https://github.com/enjoy-digital/litex-boards>           | 1d8f0a9 |
 | <https://github.com/m-labs/migen>                         | 40b1092 |
 | <https://github.com/nmigen/nmigen>                        | 490fca5 |
 | <https://github.com/litex-hub/pythondata-cpu-vexriscv>    | 16c5dde |

minitests/litex/nexys_video_sata/requirements.txt

@@ -1,10 +1,10 @@
 # Litex
--e git+https://github.com/enjoy-digital/litex@e8cfe3b6ea4d8fbea0080d5cae4302169fc804cb#egg=litex
+-e git+https://github.com/enjoy-digital/litex@7abfbd9825188d1f6d97453838e18ed7af5526a7#egg=litex
 -e git+https://github.com/enjoy-digital/litedram@ab2423e3dd06783d80fef7aeb43b7c5513c1f2f0#egg=litedram
 -e git+https://github.com/enjoy-digital/liteeth@7448170390ddf4b7c353ae10932377255581c25a#egg=liteeth
 -e git+https://github.com/enjoy-digital/liteiclink@0980a7cf4ffcb0b69a84fa0343a66180408b2a91#egg=liteiclink
 -e git+https://github.com/enjoy-digital/litesata@fae9f8d5b7b6d4c6a0a93b496bd15db5201d14f7#egg=litesata
--e git+https://github.com/litex-hub/litex-boards@bee71da7746c6fda0d4e1942452510e11f06c14a#egg=litex_boards
+-e git+https://github.com/litex-hub/litex-boards@1d8f0a98298e0ed9d5fed08daa7c25aded7ecbb4#egg=litex_boards
 
 # Migen and nMigen
 -e git+https://github.com/m-labs/migen@40b1092a05ec7659c42c8087b0c229dcfb5d9ca1#egg=migen

settings/artix7/resources.yaml

@@ -26,6 +26,15 @@
     4: "V14"
     5: "U14"
     6: "U16"
+"xc7a100tfgg484-2":
+  pins:
+    0: "J19"
+    1: "E14"
+    2: "E13"
+    3: "U6"
+    4: "V4"
+    5: "W5"
+    6: "V5"
 "xc7a100tcsg324-1":
   pins:
     0: "N15"