docs: Import README add give fuzzers structures.

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

docs/Makefile

@@ -23,17 +23,18 @@ fuzzers-links:
 	@cd db_dev_process/fuzzers; rm -f *.md
 	@cd db_dev_process/fuzzers; \
 		for i in ../../../fuzzers/*; do \
+			n=$$(basename $$i | sed -e's/^[0-9][0-9][0-9]-//'); \
 			if [ ! -d $$i ]; then \
 				continue; \
 			fi; \
 			if [ -e $$i/README.md ]; then \
 				echo "Linking $$i/README.md"; \
-				ln -s $$i/README.md $$(basename $$i).md; \
+				ln -s $$i/README.md $${n}.md; \
 			else \
 				echo "Missing $$i/README.md"; \
-				echo "# $$(basename $$i)" 	> $$(basename $$i).md; \
+				echo "# $$n Fuzzer"		>  $${n}.md; \
-				echo "" 			>> $$(basename $$i).md; \
+				echo "" 			>> $${n}.md; \
-				echo "Missing README.md!" 	>> $$(basename $$i).md; \
+				echo "Missing README.md!" 	>> $${n}.md; \
 			fi; \
 		done
 
@@ -41,17 +42,18 @@ minitests-links:
 	@cd db_dev_process/minitests; rm -f *.md
 	@cd db_dev_process/minitests; \
 		for i in ../../../minitests/*; do \
+			n=$$(basename $$i | sed -e's/^[0-9][0-9][0-9]-//'); \
 			if [ ! -d $$i ]; then \
 				continue; \
 			fi; \
 			if [ -e $$i/README.md ]; then \
 				echo "Linking $$i/README.md"; \
-				ln -s $$i/README.md $$(basename $$i).md; \
+				ln -s $$i/README.md $${n}.md; \
 			else \
 				echo "Missing $$i/README.md"; \
-				echo "# $$(basename $$i)" 	> $$(basename $$i).md; \
+				echo "# $$n Minitest"		>  $${n}.md; \
-				echo "" 			>> $$(basename $$i).md; \
+				echo "" 			>> $${n}.md; \
-				echo "Missing README.md!" 	>> $$(basename $$i).md; \
+				echo "Missing README.md!" 	>> $${n}.md; \
 			fi; \
 		done
 

docs/db_dev_process/fuzzers/005-tilegrid.md

@@ -1 +0,0 @@
-../../../fuzzers/005-tilegrid/README.md

docs/db_dev_process/parts.rst

@@ -1,17 +1,6 @@
-Overview
-=========
-
-`SymbiFlow Architecture Definitions <https://github.com/SymbiFlow/symbiflow-arch-defs>`_
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-This is where we describe the logical components in a device to VPR.
-
-* VtR stands for `Verilog to Routing <https://verilogtorouting.org/>`_,
-* VPR stands for VtR Place and Route.
-* VtR also has its own synthesis tool called ODIN-II, but we are using `Yosys <https://github.com/YosysHQ/yosys>`_ instead of that.
-
 
 Fuzzers
-^^^^^^^
+=======
 Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
 This is how the contents of the database are generated.
 
@@ -25,15 +14,95 @@ By looking at all the resulting specimens, you can correlate which bits in which
 
 Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.
 
+Configurable Logic Blocks (CLB)
+-------------------------------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/*clb*
+
+Block RAM (BRAM)
+----------------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/*bram*
+
+Input / Output (IOB)
+--------------------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/*iob*
+
+Clocking (CMT, PLL, BUFG, etc)
+------------------------------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/*clk*
+   fuzzers/*cmt*
+
+Programmable Interconnect Points (PIPs)
+---------------------------------------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/*int*
+   fuzzers/*pip*
+
+Hard Block Fuzzers
+------------------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/*xadc
+
+Grid and Wire
+-------------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/tilegrid
+   fuzzers/tileconn
+   fuzzers/ordered_wires
+   fuzzers/get_counts
+   fuzzers/dump_all
+
+Timing
+------
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   fuzzers/timing
+
+All Fuzzers
+-----------
+
 .. toctree::
    :maxdepth: 1
-   :caption: Current Fuzzers
    :glob:
 
    fuzzers/*
 
 Minitests
-^^^^^^^^^
+=========
 
 Minitests are experiments to figure out how things work. They allow us to understand how to better write new fuzzers.
 
@@ -45,12 +114,8 @@ Minitests are experiments to figure out how things work. They allow us to unders
    minitests/*
 
 Tools
-^^^^^
+=====
 
 `SymbiFlow/prjxray/tools/`
 
 Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers.
-
-SymbiFlow/prjxray/minitests/roi_harness
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler).

docs/db_dev_process/readme.md

@@ -0,0 +1 @@
+../../README.md

docs/index.rst

@@ -24,10 +24,11 @@ to develop a free and open Verilog to bitstream toolchain for these devices.
    architecture/glossary
 
 .. toctree::
-   :maxdepth: 2
+   :maxdepth: 1
    :caption: Database Development Process
 
-   db_dev_process/overview
+   db_dev_process/readme
+   db_dev_process/parts
 
 .. toctree::
    :maxdepth: 2