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ffprim: fix remaining issues 

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster 2017-11-28 16:25:01 -08:00 committed by Tim 'mithro' Ansell
parent 1e2041c447
commit ee3613e047
5 changed files with 188 additions and 117 deletions
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72
experiments/ffprim/README.txt
View File

@ -10,31 +10,53 @@ More research needed
CLB.SLICE_X0.AFF.FF_INV_CLK 00_51 FSYNC LATCH ZRESET
CLB.SLICE_X0.FF_FDCE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 29_12 30_01 30_03 Sample 00_48 30_32 30_12
CLB.SLICE_X0.FF_FDPE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 30_01 FDPE
CLB.SLICE_X0.FF_FDRE 00_21 00_24 00_25 00_26 00_29 29_01 29_12 30_01 30_03 FDSE X
CLB.SLICE_X0.FF_FDSE 00_21 00_24 00_25 00_26 00_29 00_35 29_01 30_01 FDRE X X
CLB.SLICE_X0.FF_USED 00_21 00_24 00_25 00_26 00_29 29_01 30_01 FDCE X
CLB.SLICE_X1.AFF.FF_INV_CLK <0 candidates> LDCE X X
CLB.SLICE_X1.FF_FDCE 00_21 00_24 00_25 00_26 00_29 29_01 30_01 30_04 30_15 LDPE X
CLB.SLICE_X1.FF_FDPE 00_21 00_24 00_25 00_26 00_29 29_01 30_01
CLB.SLICE_X1.FF_FDRE 00_21 00_24 00_25 00_26 00_29 00_31 29_01 30_01 30_04 30_15
CLB.SLICE_X1.FF_FDSE 00_21 00_24 00_25 00_26 00_29 00_31 29_01 30_01
CLB.SLICE_X1.FF_USED 00_21 00_24 00_25 00_26 00_29 29_01 30_01
Following bits are always present with a FF
00_21 CLB.SLICE_X0.A5FF.ZINIT 31_06
00_24 CLB.SLICE_X0.A5FF.ZRESET 01_07
00_25 CLB.SLICE_X0.AFF.ZINIT 31_03
00_26 CLB.SLICE_X0.AFF.ZRESET 30_12
00_29 CLB.SLICE_X0.B5FF.ZINIT 31_22
29_01 CLB.SLICE_X0.B5FF.ZRESET 01_19
30_01 CLB.SLICE_X0.BFF.ZINIT 31_28
Interesting bits are then CLB.SLICE_X0.BFF.ZRESET 30_30
CLB.SLICE_X0.FF_FDCE 00_35 29_12 30_03 CLB.SLICE_X0.C5FF.ZINIT 31_41
CLB.SLICE_X0.FF_FDPE 00_35 CLB.SLICE_X0.C5FF.ZRESET 01_47
CLB.SLICE_X0.FF_FDSE 00_35 CLB.SLICE_X0.CFF.ZINIT 31_33
CLB.SLICE_X0.FF_FDRE 29_12 30_03 CLB.SLICE_X0.CFF.ZRESET 30_33
CLB.SLICE_X0.CLKINV 01_51
CLB.SLICE_X0.D5FF.ZINIT 31_51
CLB.SLICE_X0.D5FF.ZRESET 01_55
CLB.SLICE_X0.DFF.ZINIT 31_58
CLB.SLICE_X0.DFF.ZRESET 30_50
CLB.SLICE_X0.FFSYNC 00_48
CLB.SLICE_X0.LATCH 30_32
CLB.SLICE_X1.A5FF.ZINIT 31_05
CLB.SLICE_X1.A5FF.ZRESET 01_03
CLB.SLICE_X1.AFF.ZINIT 31_04
CLB.SLICE_X1.AFF.ZRESET 31_15
CLB.SLICE_X1.B5FF.ZINIT 31_23
CLB.SLICE_X1.B5FF.ZRESET 00_16
CLB.SLICE_X1.BFF.ZINIT 31_29
CLB.SLICE_X1.BFF.ZRESET 31_30
CLB.SLICE_X1.C5FF.ZINIT 31_42
CLB.SLICE_X1.C5FF.ZRESET 00_44
CLB.SLICE_X1.CFF.ZINIT 31_34
CLB.SLICE_X1.CFF.ZRESET 30_34
CLB.SLICE_X1.CLKINV 00_52
CLB.SLICE_X1.D5FF.ZINIT 31_52
CLB.SLICE_X1.D5FF.ZRESET 00_56
CLB.SLICE_X1.DFF.ZINIT 31_59
CLB.SLICE_X1.DFF.ZRESET 31_50
CLB.SLICE_X1.FFSYNC 01_31
CLB.SLICE_X1.LATCH 31_32

111
experiments/ffprim/generate.py
View File

@ -1,5 +1,14 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
'''
FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear
FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset
FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset
FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set
LDCE Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable
LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable
'''
from prims import * from prims import *
import sys, re import sys, re
@ -18,6 +27,29 @@ def ones(l):
ret.append(x + '_1') ret.append(x + '_1')
return ret return ret
def loadtop():
'''
i,prim,loc,bel
0,FDPE,SLICE_X12Y100,C5FF
1,FDPE,SLICE_X15Y100,A5FF
2,FDPE_1,SLICE_X16Y100,B5FF
3,LDCE_1,SLICE_X17Y100,BFF
'''
f = open('top.txt', 'r')
f.readline()
ret = {}
for l in f:
i,prim,loc,bel,init = l.split(",")
i = int(i)
init = int(init)
ret[loc] = (i,prim,loc,bel,init)
return ret
top = loadtop()
def vs2i(s):
return {"1'b0": 0, "1'b1": 1}[s]
print("Loading tags from design.txt") print("Loading tags from design.txt")
with open("design.txt", "r") as f: with open("design.txt", "r") as f:
for line in f: for line in f:
@ -33,6 +65,7 @@ with open("design.txt", "r") as f:
grid_x = line[2] grid_x = line[2]
grid_y = line[3] grid_y = line[3]
# Other code uses BEL name # Other code uses BEL name
# SLICE_X12Y137/D5FF
site_ff_name = line[4] site_ff_name = line[4]
site, ff_name = site_ff_name.split('/') site, ff_name = site_ff_name.split('/')
ff_type = line[5] ff_type = line[5]
@ -46,68 +79,42 @@ with open("design.txt", "r") as f:
# 1'b1 # 1'b1
# cinv = int(line[9][-1]) # cinv = int(line[9][-1])
cinv = int(line[9]) cinv = int(line[9])
init = vs2i(line[10])
#init = int(line[10])
# A B C D
which = ff_name[0] which = ff_name[0]
# Reduced test for now # LUT6 vs LUT5 FF
#if ff_name != 'AFF':
# continue
is5 = '5' in ff_name is5 = '5' in ff_name
#segmk.addtag(site, "FF_USED", used)
if 1:
# If unused mark all primitives as not present
# Otherwise mark the primitive we are using
if used: if used:
segmk.addtag(site, "%s.%s" % (ff_name, cel_prim), 1) segmk.addtag(site, "%s.ZINIT" % ff_name, 1 ^ init)
# CLKINV turns out to be more complicated than origianlly thought
if isff(cel_prim):
segmk.addtag(site, "CLKINV", cinv)
else: else:
for ffprim in ffprims: segmk.addtag(site, "CLKINV", 1 ^ cinv)
# FF's don't do 5's
if isff(ffprim) or (isl(ffprim) and not is5):
segmk.addtag(site, "%s.%s" % (ff_name, ffprim), 0)
# Theory: # Synchronous vs asynchronous FF
# FDPE represents none of the FF specific bits used # Unlike most bits, shared between all CLB FFs
# FDRE has all of the bits used
if 0:
# If unused mark all primitives as not present
# Otherwise mark the primitive we are using
# Should yield 3 bits
if used:
if cel_prim == 'FDPE':
segmk.addtag(site, "%s.PRIM" % ff_name, 0)
if cel_prim == 'FDRE':
segmk.addtag(site, "%s.PRIM" % ff_name, 1)
# FF specific test
# Theory: FDSE and FDCE are the most and least encoded FF's
if 1:
# If unused mark all primitives as not present
# Otherwise mark the primitive we are using
# Should yield 3 bits
if used and isff(cel_prim):
# PRIM1 is now FFSYNC
#segmk.addtag(site, "%s.PRIM1" % ff_name,
# cel_prim in ('FDSE', 'FDRE'))
segmk.addtag(site, "%s.PRIM2" % ff_name,
cel_prim in ('FDCE', 'FDRE'))
# Theory: there are some common enable bits
'''
00_48 30_32 30_12 31_03
FDPE
FDSE X
FDRE X X X
FDCE X X
LDCE X X X
LDPE X
00_48 is shared between all X0 FFs
'''
if 1 and used:
segmk.addtag(site, "FFSYNC", segmk.addtag(site, "FFSYNC",
cel_prim in ('FDSE', 'FDRE')) cel_prim in ('FDSE', 'FDRE'))
# Latch bit
# Only applies to LUT6 (non-5) FF's
if not is5:
segmk.addtag(site, "LATCH", isl(cel_prim))
'''
On name:
The primitives you listed have a control input to set the FF value to zero (clear/reset),
the other three primitives have a control input that sets the FF value to one.
Z => inversion
'''
segmk.addtag(site, "%s.ZRESET" % ff_name,
cel_prim in ('FDRE', 'FDCE', 'LDCE'))
segmk.compile() segmk.compile()
segmk.write() segmk.write()

6
experiments/ffprim/generate.tcl
View File

@ -41,6 +41,7 @@ foreach ff $ffs {
set bel_type [get_property TYPE $ff] set bel_type [get_property TYPE $ff]
set used [get_property IS_USED $ff] set used [get_property IS_USED $ff]
set usedstr "" set usedstr ""
if $used { if $used {
set ffc [get_cells -of_objects $ff] set ffc [get_cells -of_objects $ff]
set cell_bel [get_property BEL $ffc] set cell_bel [get_property BEL $ffc]
@ -52,7 +53,10 @@ foreach ff $ffs {
# Latches have gate pin # Latches have gate pin
set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}] set cpin [get_pins -of_objects $ffc -filter {REF_PIN_NAME == C || REF_PIN_NAME == G}]
set cinv [get_property IS_INVERTED $cpin] set cinv [get_property IS_INVERTED $cpin]
set usedstr "$cell_bel $ref_name $cinv"
set init [get_property INIT $ffc]
set usedstr "$cell_bel $ref_name $cinv $init"
} }
puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr" puts $fp "$type $tile $grid_x $grid_y $ff $bel_type $used $usedstr"
} }

15
experiments/ffprim/prims.py
View File

@ -7,6 +7,7 @@ def ones(l):
ret.append(x + '_1') ret.append(x + '_1')
return ret return ret
# The complete primitive sets
ffprims_fall = ones([ ffprims_fall = ones([
'FD', 'FD',
'FDC', 'FDC',
@ -19,12 +20,6 @@ ffprims_fall = ones([
'FDS', 'FDS',
'FDSE', 'FDSE',
]) ])
ffprims_f = [
'FDRE',
'FDSE',
'FDCE',
'FDPE',
]
ffprims_lall = ones([ ffprims_lall = ones([
'LDC', 'LDC',
'LDCE', 'LDCE',
@ -32,6 +27,14 @@ ffprims_lall = ones([
'LDPE', 'LDPE',
'LDP', 'LDP',
]) ])
# Base primitives
ffprims_f = [
'FDRE',
'FDSE',
'FDCE',
'FDPE',
]
ffprims_l = [ ffprims_l = [
'LDCE', 'LDCE',
'LDPE', 'LDPE',

99
experiments/ffprim/top.py
View File

@ -16,6 +16,9 @@ print('//SLICEY: %s' % str(SLICEY))
print('//SLICEN: %s' % str(SLICEN)) print('//SLICEN: %s' % str(SLICEN))
print('//Requested CLBs: %s' % str(CLBN)) print('//Requested CLBs: %s' % str(CLBN))
f = open("top.txt", "w")
f.write("i,prim,loc,bel,init\n")
def gen_slices(): def gen_slices():
for slicey in range(*SLICEY): for slicey in range(*SLICEY):
for slicex in range(*SLICEX): for slicex in range(*SLICEX):
@ -57,7 +60,7 @@ endmodule
slices = gen_slices() slices = gen_slices()
print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1)) print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
for i in range(CLBN): for i in range(CLBN):
ffprim = random.choice(ffprims) ffprim = random.choice(ones(ffprims))
# clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0])); # clb_FD clb_FD (.clk(clk), .din(din[ 0 +: 4]), .dout(dout[ 0]));
# clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1])); # clb_FD_1 clb_FD_1 (.clk(clk), .din(din[ 4 +: 4]), .dout(dout[ 1]));
loc = next(slices) loc = next(slices)
@ -66,10 +69,12 @@ for i in range(CLBN):
bel = random.choice(ff_bels) bel = random.choice(ff_bels)
else: else:
bel = random.choice(ff_bels_ffl) bel = random.choice(ff_bels_ffl)
init = random.choice((0, 1))
#bel = "AFF" #bel = "AFF"
print(' clb_%s' % ffprim) print(' clb_%s' % ffprim)
print(' #(.LOC("%s"), .BEL("%s"))' % (loc, bel)) print(' #(.LOC("%s"), .BEL("%s"), .INIT(%d))' % (loc, bel, init))
print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i)) print(' clb_%d (.clk(clk), .din(din[ %d +: 4]), .dout(dout[ %d]));' % (i, 4 * i, 1 * i))
f.write("%d,%s,%s,%s,%d\n" % (i, ffprim, loc, bel, init))
print('''endmodule print('''endmodule
// --------------------------------------------------------------------- // ---------------------------------------------------------------------
@ -80,7 +85,8 @@ print('''
module clb_FD (input clk, input [3:0] din, output dout); module clb_FD (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y100"; parameter LOC="SLICE_X16Y100";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FD ff ( FD ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -91,7 +97,8 @@ module clb_FD (input clk, input [3:0] din, output dout);
module clb_FD_1 (input clk, input [3:0] din, output dout); module clb_FD_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y101"; parameter LOC="SLICE_X16Y101";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FD_1 ff ( FD_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -102,7 +109,8 @@ module clb_FD_1 (input clk, input [3:0] din, output dout);
module clb_FDC (input clk, input [3:0] din, output dout); module clb_FDC (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y102"; parameter LOC="SLICE_X16Y102";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDC ff ( FDC ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -114,7 +122,8 @@ module clb_FDC (input clk, input [3:0] din, output dout);
module clb_FDC_1 (input clk, input [3:0] din, output dout); module clb_FDC_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y103"; parameter LOC="SLICE_X16Y103";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDC_1 ff ( FDC_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -126,7 +135,8 @@ module clb_FDC_1 (input clk, input [3:0] din, output dout);
module clb_FDCE (input clk, input [3:0] din, output dout); module clb_FDCE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y104"; parameter LOC="SLICE_X16Y104";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDCE ff ( FDCE ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -139,7 +149,8 @@ module clb_FDCE (input clk, input [3:0] din, output dout);
module clb_FDCE_1 (input clk, input [3:0] din, output dout); module clb_FDCE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y105"; parameter LOC="SLICE_X16Y105";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDCE_1 ff ( FDCE_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -152,7 +163,8 @@ module clb_FDCE_1 (input clk, input [3:0] din, output dout);
module clb_FDE (input clk, input [3:0] din, output dout); module clb_FDE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y106"; parameter LOC="SLICE_X16Y106";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDE ff ( FDE ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -164,7 +176,8 @@ module clb_FDE (input clk, input [3:0] din, output dout);
module clb_FDE_1 (input clk, input [3:0] din, output dout); module clb_FDE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y107"; parameter LOC="SLICE_X16Y107";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDE_1 ff ( FDE_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -176,7 +189,8 @@ module clb_FDE_1 (input clk, input [3:0] din, output dout);
module clb_FDP (input clk, input [3:0] din, output dout); module clb_FDP (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y108"; parameter LOC="SLICE_X16Y108";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDP ff ( FDP ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -188,7 +202,8 @@ module clb_FDP (input clk, input [3:0] din, output dout);
module clb_FDP_1 (input clk, input [3:0] din, output dout); module clb_FDP_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y109"; parameter LOC="SLICE_X16Y109";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDP_1 ff ( FDP_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -200,7 +215,8 @@ module clb_FDP_1 (input clk, input [3:0] din, output dout);
module clb_FDPE (input clk, input [3:0] din, output dout); module clb_FDPE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y110"; parameter LOC="SLICE_X16Y110";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDPE ff ( FDPE ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -213,7 +229,8 @@ module clb_FDPE (input clk, input [3:0] din, output dout);
module clb_FDPE_1 (input clk, input [3:0] din, output dout); module clb_FDPE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y111"; parameter LOC="SLICE_X16Y111";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDPE_1 ff ( FDPE_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -226,7 +243,8 @@ module clb_FDPE_1 (input clk, input [3:0] din, output dout);
module clb_FDR (input clk, input [3:0] din, output dout); module clb_FDR (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y112"; parameter LOC="SLICE_X16Y112";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDR ff ( FDR ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -238,7 +256,8 @@ module clb_FDR (input clk, input [3:0] din, output dout);
module clb_FDR_1 (input clk, input [3:0] din, output dout); module clb_FDR_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y113"; parameter LOC="SLICE_X16Y113";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDR_1 ff ( FDR_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -250,7 +269,8 @@ module clb_FDR_1 (input clk, input [3:0] din, output dout);
module clb_FDRE (input clk, input [3:0] din, output dout); module clb_FDRE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y114"; parameter LOC="SLICE_X16Y114";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDRE ff ( FDRE ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -263,7 +283,8 @@ module clb_FDRE (input clk, input [3:0] din, output dout);
module clb_FDRE_1 (input clk, input [3:0] din, output dout); module clb_FDRE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y115"; parameter LOC="SLICE_X16Y115";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDRE_1 ff ( FDRE_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -276,7 +297,8 @@ module clb_FDRE_1 (input clk, input [3:0] din, output dout);
module clb_FDS (input clk, input [3:0] din, output dout); module clb_FDS (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y116"; parameter LOC="SLICE_X16Y116";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDS ff ( FDS ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -288,7 +310,8 @@ module clb_FDS (input clk, input [3:0] din, output dout);
module clb_FDS_1 (input clk, input [3:0] din, output dout); module clb_FDS_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y117"; parameter LOC="SLICE_X16Y117";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDS_1 ff ( FDS_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -300,7 +323,8 @@ module clb_FDS_1 (input clk, input [3:0] din, output dout);
module clb_FDSE (input clk, input [3:0] din, output dout); module clb_FDSE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y118"; parameter LOC="SLICE_X16Y118";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDSE ff ( FDSE ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -313,7 +337,8 @@ module clb_FDSE (input clk, input [3:0] din, output dout);
module clb_FDSE_1 (input clk, input [3:0] din, output dout); module clb_FDSE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y119"; parameter LOC="SLICE_X16Y119";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
FDSE_1 ff ( FDSE_1 ff (
.C(clk), .C(clk),
.Q(dout), .Q(dout),
@ -328,7 +353,8 @@ module clb_FDSE_1 (input clk, input [3:0] din, output dout);
module clb_LDC (input clk, input [3:0] din, output dout); module clb_LDC (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y120"; parameter LOC="SLICE_X16Y120";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDC ff ( LDC ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),
@ -339,7 +365,8 @@ module clb_LDC (input clk, input [3:0] din, output dout);
module clb_LDC_1 (input clk, input [3:0] din, output dout); module clb_LDC_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y121"; parameter LOC="SLICE_X16Y121";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDC_1 ff ( LDC_1 ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),
@ -351,7 +378,8 @@ module clb_LDC_1 (input clk, input [3:0] din, output dout);
module clb_LDCE (input clk, input [3:0] din, output dout); module clb_LDCE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y122"; parameter LOC="SLICE_X16Y122";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDCE ff ( LDCE ff (
.G(~clk), .G(~clk),
//NOTE: diagram shows two outputs. Error? //NOTE: diagram shows two outputs. Error?
@ -364,7 +392,8 @@ module clb_LDCE (input clk, input [3:0] din, output dout);
module clb_LDCE_1 (input clk, input [3:0] din, output dout); module clb_LDCE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y123"; parameter LOC="SLICE_X16Y123";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDCE_1 ff ( LDCE_1 ff (
.G(~clk), .G(~clk),
//NOTE: diagram shows two outputs. Error? //NOTE: diagram shows two outputs. Error?
@ -378,7 +407,8 @@ module clb_LDCE_1 (input clk, input [3:0] din, output dout);
module clb_LDE (input clk, input [3:0] din, output dout); module clb_LDE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y124"; parameter LOC="SLICE_X16Y124";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDE ff ( LDE ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),
@ -389,7 +419,8 @@ module clb_LDE (input clk, input [3:0] din, output dout);
module clb_LDE_1 (input clk, input [3:0] din, output dout); module clb_LDE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y125"; parameter LOC="SLICE_X16Y125";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDE_1 ff ( LDE_1 ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),
@ -401,7 +432,8 @@ module clb_LDE_1 (input clk, input [3:0] din, output dout);
module clb_LDP (input clk, input [3:0] din, output dout); module clb_LDP (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y126"; parameter LOC="SLICE_X16Y126";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDP ff ( LDP ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),
@ -412,7 +444,8 @@ module clb_LDP (input clk, input [3:0] din, output dout);
module clb_LDP_1 (input clk, input [3:0] din, output dout); module clb_LDP_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y127"; parameter LOC="SLICE_X16Y127";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDP_1 ff ( LDP_1 ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),
@ -424,7 +457,8 @@ module clb_LDP_1 (input clk, input [3:0] din, output dout);
module clb_LDPE (input clk, input [3:0] din, output dout); module clb_LDPE (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y128"; parameter LOC="SLICE_X16Y128";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDPE ff ( LDPE ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),
@ -436,7 +470,8 @@ module clb_LDPE (input clk, input [3:0] din, output dout);
module clb_LDPE_1 (input clk, input [3:0] din, output dout); module clb_LDPE_1 (input clk, input [3:0] din, output dout);
parameter LOC="SLICE_X16Y129"; parameter LOC="SLICE_X16Y129";
parameter BEL="AFF"; parameter BEL="AFF";
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *) parameter INIT=1'b0;
(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH, INIT=INIT *)
LDPE_1 ff ( LDPE_1 ff (
.G(~clk), .G(~clk),
.Q(dout), .Q(dout),