fuzzers: 007: add routing BELs fuzzer

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

fuzzers/007-timing/routing-bels/Makefile

@@ -0,0 +1,17 @@
+all: build/slicel.json build/slicem.json
+
+clean:
+	rm -rf build
+
+build/slicel.json: build/slicel.txt
+	python3 tim2sdf.py --timings build/slicel.txt --json build/slicel.json
+
+build/slicem.json: build/slicem.txt
+	python3 tim2sdf.py --timings build/slicem.txt --json build/slicem.json
+
+build/slicel.txt build/slicem.txt:
+	bash runme.sh
+
+cleandb:
+	rm -rf ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/timings
+

fuzzers/007-timing/routing-bels/runme.sh

@@ -0,0 +1,13 @@
+#!/bin/bash
+
+set -ex
+
+# Create build dir
+export SRC_DIR=$PWD
+export BUILD_DIR=build
+
+mkdir -p $BUILD_DIR
+cd $BUILD_DIR
+
+${XRAY_VIVADO} -mode batch -source $SRC_DIR/runme.tcl
+test -z "$(fgrep CRITICAL vivado.log)" && touch run.ok

fuzzers/007-timing/routing-bels/runme.tcl

@@ -0,0 +1,62 @@
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc create_design {} {
+
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog $::env(SRC_DIR)/top.v
+    synth_design -top top -flatten_hierarchy none
+
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports di]
+    set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports do]
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+}
+
+proc place_and_route_design {} {
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+}
+
+proc dump_model_timings {timing_fp models} {
+
+    set properties [list "DELAY" "FAST_MAX" "FAST_MIN" "SLOW_MAX" "SLOW_MIN"]
+
+    foreach model $models {
+        set timing_line {}
+        lappend timing_line "$model"
+        foreach property $properties {
+            set value [get_property $property [get_speed_models -patterns $model]]
+            lappend timing_line "$property:$value"
+        }
+
+        puts $timing_fp $timing_line
+    }
+}
+
+proc dump {} {
+
+    set slicel_fp [open "slicel.txt" w]
+    set slicem_fp [open "slicem.txt" w]
+    set slicel_speed_models [get_speed_models -patterns *_sl_*]
+    set slicem_speed_models [get_speed_models -patterns *_sm_*]
+
+    dump_model_timings $slicel_fp $slicel_speed_models
+    dump_model_timings $slicem_fp $slicem_speed_models
+
+    close $slicel_fp
+    close $slicem_fp
+}
+
+proc run {} {
+    create_design
+    place_and_route_design
+    dump
+    write_bitstream -force design.bit
+}
+
+run

fuzzers/007-timing/routing-bels/tim2sdf.py

@@ -0,0 +1,42 @@
+#!/usr/bin/env python3
+
+import argparse
+import json
+
+
+def read_raw_timings(fin):
+
+    timings = dict()
+    with open(fin, "r") as f:
+        for line in f:
+
+            raw_data = line.split()
+            speed_model = raw_data[0]
+
+            if speed_model.startswith('bel_d_'):
+                speed_model = speed_model[6:]
+
+            if speed_model not in timings:
+                timings[speed_model] = dict()
+
+            # each timing entry reports 5 delays
+            for d in range(0, 5):
+                (t, v) = raw_data[d + 1].split(':')
+                timings[speed_model][t] = v
+
+    return timings
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument('--timings', type=str, help='Raw timing input file')
+    parser.add_argument('--json', type=str, help='json output file')
+    parser.add_argument(
+        '--debug', type=bool, default=False, help='Enable debug json dumps')
+    args = parser.parse_args()
+
+    timings = read_raw_timings(args.timings)
+    with open(args.json, 'w') as fp:
+        json.dump(timings, fp, indent=4, sort_keys=True)
+
+if __name__ == '__main__':
+    main()

fuzzers/007-timing/routing-bels/top.v

@@ -0,0 +1,5 @@
+module top(input di, output do);
+
+   assign do = di;
+
+endmodule