mirror of https://github.com/openXC7/prjxray.git
Merge pull request #621 from litghost/kintex_tilegrid_int
Add XADC INT and ICAP INT fuzzers to solve 2 of 4 missing INT columns.
This commit is contained in:
litghost
GitHub
commit
ebe9a457cd
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@ -11,6 +11,8 @@ TILEGRID_TDB_DEPENDENCIES += clb/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += clb_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += dsp/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += fifo_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += cfg_int/build/segbits_tilegrid.tdb
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TILEGRID_TDB_DEPENDENCIES += monitor_int/build/segbits_tilegrid.tdb
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GENERATE_FULL_ARGS=
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ifeq (${XRAY_DATABASE}, zynq7)
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@ -66,6 +68,9 @@ ps7_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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monitor/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd monitor && $(MAKE)
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monitor_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd monitor_int && $(MAKE)
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bram/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd bram && $(MAKE)
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@ -84,6 +89,9 @@ dsp_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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fifo_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd fifo_int && $(MAKE)
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cfg_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json
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cd cfg_int && $(MAKE)
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build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
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python3 add_tdb.py \
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--fn-in build/basicdb/tilegrid.json \
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@ -114,6 +122,8 @@ clean:
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cd dsp_int && $(MAKE) clean
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cd fifo_int && $(MAKE) clean
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cd monitor && $(MAKE) clean
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cd monitor_int && $(MAKE) clean
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cd cfg_int && $(MAKE) clean
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.PHONY: database pushdb clean run
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@ -90,6 +90,8 @@ def run(fn_in, fn_out, verbose=False):
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("dsp_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("fifo_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("ps7_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("cfg_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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("monitor_int/build/segbits_tilegrid.tdb", int_frames, int_words),
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]
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for (tdb_fn, frames, words) in tdb_fns:
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@ -0,0 +1,3 @@
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N ?= 4
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GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 15 --dword 0"
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include ../fuzzaddr/common.mk
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@ -0,0 +1,19 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,118 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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if gridinfo.tile_type != 'CFG_CENTER_MID':
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continue
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sites = {}
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for site_name, site_type in gridinfo.sites.items():
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if site_type not in sites:
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sites[site_type] = []
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sites[site_type].append(site_name)
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for site_type in sites:
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sites[site_type].sort()
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int_grid_x = loc.grid_x + 3
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int_tile_type = 'INT_L'
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int_tile_locs = []
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for dy in range(-9, 12):
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# Skip the VBREAK tile.
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if dy != 6:
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int_tile_locs.append((int_grid_x, loc.grid_y + dy), )
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int_tiles = []
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for int_tile_loc in int_tile_locs:
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int_gridinfo = grid.gridinfo_at_loc(int_tile_loc)
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assert int_gridinfo.tile_type == int_tile_type, (
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int_gridinfo.tile_type, int_tile_type)
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int_tiles.append(grid.tilename_at_loc(int_tile_loc))
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yield tile_name, sites, int_tiles
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def write_params(params):
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pinstr = 'tile,val\n'
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for tile, (val) in sorted(params.items()):
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pinstr += '%s,%s\n' % (tile, val)
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open('params.csv', 'w').write(pinstr)
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def run():
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print('''
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module top();
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''')
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sites = list(gen_sites())
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# Only on CFG_CENTER_MID expected.
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assert len(sites) == 1
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tile_name, sites, int_tiles = sites[0]
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assert len(sites['ICAP']) == 2, len(sites['ICAP'])
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# int_tiles[6]:
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# IMUX43 -> ICAP1_I31 = 0
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# IMUX42 -> ICAP1_I30 = toggle 0/1
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# int_tiles[7]:
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# IMUX43 -> ICAP1_I15 = 0
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# IMUX42 -> ICAP1_I14 = toggle 0/1
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# int_tiles[8]:
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# IMUX43 -> ICAP1_CSIB = 0
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# IMUX42 -> ICAP1_RDWRB = toggle 0/1
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ICAP1_I30 = random.randint(0, 1)
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ICAP1_I14 = random.randint(0, 1)
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ICAP1_RDWRB = random.randint(0, 1)
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params = {}
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params[int_tiles[6]] = ICAP1_I30
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params[int_tiles[7]] = ICAP1_I14
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params[int_tiles[8]] = ICAP1_RDWRB
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print(
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"""
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wire [31:0] icap_i_{site};
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wire icap_rdwrd_{site};
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wire icap_csib_{site};
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assign icap_i_{site}[31] = 0;
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assign icap_i_{site}[30] = {ICAP1_I30};
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assign icap_i_{site}[15] = 0;
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assign icap_i_{site}[14] = {ICAP1_I14};
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assign icap_csib_{site} = 0;
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assign icap_rdwrb_{site} = {ICAP1_RDWRB};
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(* KEEP, DONT_TOUCH, LOC = "{site}" *)
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ICAPE2 icap_{site} (
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.I(icap_i_{site}),
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.RDWRB(icap_rdwrb_{site}),
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.CSIB(icap_csib_{site})
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);
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""".format(
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site=sites['ICAP'][1],
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ICAP1_I30=ICAP1_I30,
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ICAP1_I14=ICAP1_I14,
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ICAP1_RDWRB=ICAP1_RDWRB))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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@ -0,0 +1,3 @@
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N ?= 4
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GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 15 --dword 0"
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include ../fuzzaddr/common.mk
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@ -0,0 +1,19 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,102 @@
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray.db import Database
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def gen_sites():
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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found_xadc = False
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['XADC']:
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found_xadc = True
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break
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if not found_xadc:
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continue
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int_grid_x = loc.grid_x + 3
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int_tile_type = 'INT_L'
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int_tile_locs = []
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for dy in range(-1, 1):
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int_tile_locs.append((int_grid_x, loc.grid_y + dy), )
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int_tiles = []
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for int_tile_loc in int_tile_locs:
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int_gridinfo = grid.gridinfo_at_loc(int_tile_loc)
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assert int_gridinfo.tile_type == int_tile_type, (
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int_gridinfo.tile_type, int_tile_type)
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int_tiles.append(grid.tilename_at_loc(int_tile_loc))
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yield tile_name, int_tiles
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def write_params(params):
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pinstr = 'tile,val\n'
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for tile, (val) in sorted(params.items()):
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pinstr += '%s,%s\n' % (tile, val)
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open('params.csv', 'w').write(pinstr)
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def run():
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print('''
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module top();
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''')
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sites = list(gen_sites())
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# Only on CFG_CENTER_MID expected.
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assert len(sites) == 1
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tile_name, int_tiles = sites[0]
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# int_tiles[0]:
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# IMUX43 -> XADC_CONVST = 0
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# IMUX42 -> XADC_DWE = toggle 0/1
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# int_tiles[1]:
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# IMUX43 -> XADC_DI15 = 0
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# IMUX42 -> XADC_DI14 = toggle 0/1
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DWE = random.randint(0, 1)
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DI14 = random.randint(0, 1)
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params = {}
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params[int_tiles[0]] = DWE
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params[int_tiles[1]] = DI14
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print(
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"""
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wire [15:0] di;
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wire dwe;
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wire convst;
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assign convst = 0;
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assign dwe = {DWE};
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assign di[15] = 0;
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assign di[14] = {DI14};
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(* KEEP, DONT_TOUCH *)
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XADC xadc (
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.DI(di),
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.DWE(dwe),
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.CONVST(convst)
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);
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""".format(
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DWE=DWE,
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DI14=DI14,
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))
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print("endmodule")
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write_params(params)
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if __name__ == '__main__':
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run()
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