mirror of https://github.com/openXC7/prjxray.git
Add fuzzers/055-gnd
Signed-off-by: Clifford Wolf <clifford@clifford.at> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
Clifford Wolf
Tim 'mithro' Ansell
parent
ba705be9ae
commit
e960329668
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/filtered_seg_int_l.segbits
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/filtered_seg_int_r.segbits
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/pattern_l.txt
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/pattern_r.txt
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/piplist.dcp
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/piplist/
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/pips_int_l.txt
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/pips_int_r.txt
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/seg_int_l.segbits
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/seg_int_r.segbits
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/specimen_[0-9][0-9][0-9]/
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/todo.txt
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/vivado*
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@ -0,0 +1,31 @@
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N := 10
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_l.segbits $(addsuffix /segdata_clbl[lm]_l.txt,$(SPECIMENS))
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${XRAY_SEGMATCH} -m 5 -M 15 -o seg_int_r.segbits $(addsuffix /segdata_clbl[lm]_r.txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} int_l seg_int_l.segbits
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${XRAY_MERGEDB} int_r seg_int_r.segbits
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${XRAY_DBFIXUP}
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$(SPECIMENS_OK): todo.txt
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bash generate.sh $(subst /OK,,$@)
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touch $@
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todo.txt:
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echo "INT_L.GFAN0.GND_WIRE" > todo.txt
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echo "INT_L.GFAN1.GND_WIRE" >> todo.txt
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echo "INT_R.GFAN0.GND_WIRE" >> todo.txt
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echo "INT_R.GFAN1.GND_WIRE" >> todo.txt
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clean:
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rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
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rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
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rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
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.PHONY: database pushdb clean
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#!/usr/bin/env python3
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import sys, os, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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tiledata = dict()
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pipdata = dict()
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ignpip = set()
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print("Loading tags from design.txt.")
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with open("design.txt", "r") as f:
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for line in f:
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tile, pip, src, dst, pnum, pdir = line.split()
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_, pip = pip.split(".")
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_, src = src.split("/")
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_, dst = dst.split("/")
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pnum = int(pnum)
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pdir = int(pdir)
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if tile not in tiledata:
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tiledata[tile] = {
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"pips": set(),
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"srcs": set(),
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"dsts": set()
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}
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if pip in pipdata:
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assert pipdata[pip] == (src, dst)
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else:
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pipdata[pip] = (src, dst)
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tiledata[tile]["pips"].add(pip)
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tiledata[tile]["srcs"].add(src)
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tiledata[tile]["dsts"].add(dst)
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if pdir == 0:
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tiledata[tile]["srcs"].add(dst)
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tiledata[tile]["dsts"].add(src)
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if pnum == 1 or pdir == 0 or not re.match(r"^(VCC|GND)_WIRE$", src):
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ignpip.add(pip)
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for tile, pips_srcs_dsts in tiledata.items():
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pips = pips_srcs_dsts["pips"]
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srcs = pips_srcs_dsts["srcs"]
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dsts = pips_srcs_dsts["dsts"]
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for pip, src_dst in pipdata.items():
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src, dst = src_dst
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if pip in ignpip:
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pass
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elif pip in pips:
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segmk.addtag(tile, "%s.%s" % (dst, src), 1)
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elif src_dst[1] not in dsts:
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segmk.addtag(tile, "%s.%s" % (dst, src), 0)
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segmk.compile()
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segmk.write()
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@ -0,0 +1,9 @@
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#!/bin/bash
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source ${XRAY_GENHEADER}
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vivado -mode batch -source ../generate.tcl
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${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
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python3 ../generate.py
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@ -0,0 +1,87 @@
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog ../top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o]
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create_pblock roi
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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place_design
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route_design
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# write_checkpoint -force design.dcp
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source ../../../utils/utils.tcl
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set fp [open "../todo.txt" r]
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set todo_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend todo_lines [split $line .]
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}
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close $fp
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set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]]
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set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]]
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for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} {
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set line [lindex $todo_lines $idx]
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puts "== $idx: $line"
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set tile_type [lindex $line 0]
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set dst_wire [lindex $line 1]
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set src_wire [lindex $line 2]
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if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]}
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if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]}
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set recv_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \
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-of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]]
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set mynet [create_net mynet_$idx]
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set mylut [create_cell -reference LUT1 mylut_$idx]
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set_property -dict "LOC $recv_site BEL A6LUT" $mylut
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if {$src_wire == "VCC_WIRE"} {
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set mytie [create_cell -reference VCC mytie_$idx]
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connect_net -net $mynet -objects "$mytie/P $mylut/I0"
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}
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if {$src_wire == "GND_WIRE"} {
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set mytie [create_cell -reference GND mytie_$idx]
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connect_net -net $mynet -objects "$mytie/G $mylut/I0"
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}
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route_via $mynet "$tile/$src_wire $tile/$dst_wire"
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}
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proc write_txtdata {filename} {
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puts "Writing $filename."
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set fp [open $filename w]
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set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]]
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if {$all_pips != {}} {
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puts "Dumping pips."
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foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] {
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foreach pip [filter $all_pips "TILE == $tile"] {
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set src_wire [get_wires -uphill -of_objects $pip]
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set dst_wire [get_wires -downhill -of_objects $pip]
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set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]]
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set dir_prop [get_property IS_DIRECTIONAL $pip]
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puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop"
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}
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}
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}
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close $fp
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}
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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write_txtdata design.txt
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@ -0,0 +1,3 @@
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module top (input i, output o);
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assign o = i;
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endmodule
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