Merge pull request #49 from mcmasterg/minitest_flatten_h

minitests: flatten hiearchy
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John McMaster 2018-01-17 15:21:38 -08:00 committed by GitHub
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@ -1,6 +1,6 @@
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
synth_design -top top -flatten_hierarchy none
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]