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064-gtx-channel-conf fuzzer runs and gets first results, many are still missing (zero candidates) 

Signed-off-by: Hans Baier <foss@hans-baier.de>
This commit is contained in:
Hans Baier 2024-10-29 11:17:56 +07:00
parent 51a0b43919
commit e565dae491
8 changed files with 1479 additions and 0 deletions
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65
fuzzers/064-gtx-channel-conf/Makefile Normal file
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# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
SHELL = bash
N ?= 20
BUILD_DIR = build_${XRAY_PART}
SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
FUZDIR ?= ${PWD}
CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
all: database
$(SPECIMENS_OK): $(SPECIMENS_DEPS)
mkdir -p ${BUILD_DIR}
bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
run:
$(MAKE) clean
$(MAKE) database
$(MAKE) pushdb
touch run.${XRAY_PART}.ok
clean:
rm -rf ${BUILD_DIR} run.${XRAY_PART}.ok
.PHONY: all run clean
# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
# as the index in the port bus
SPECIAL_PINS = CLKRSVD0,CLKRSVD1,GTREFCLK0,GTREFCLK1,GTNORTHREFCLK0,GTNORTHREFCLK1,GTSOUTHREFCLK0,GTSOUTHREFCLK1,RXUSRCLK,RXUSRCLK2,TXUSRCLK,TXUSRCLK2,RXOSINTID0,PMARSVDIN0,PMARSVDIN1,PMARSVDIN2,PMARSVDIN3,PMARSVDIN4,PMARSVDOUT0,PMARSVDOUT1
$(BUILD_DIR)/gtxe2_channel_ports.csv:
env FILE_NAME=$(BUILD_DIR)/gtxe2_channel_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
$(BUILD_DIR)/gtxe2_channel_ports.json: $(BUILD_DIR)/gtxe2_channel_ports.csv
python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/gtxe2_channel_pins.csv $(BUILD_DIR)/gtxe2_channel_ports.json --special-pins $(SPECIAL_PINS)
database: ${BUILD_DIR}/segbits_gtx_channelx.db $(BUILD_DIR)/gtxe2_channel_ports.json
${BUILD_DIR}/segbits_gtx_channelx.rdb: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -c 9 -o ${BUILD_DIR}/segbits_gtx_channelx.rdb $$(find $(SPECIMENS) -name "segdata_gtx_channel_[0123]*")
${BUILD_DIR}/segbits_gtx_channelx.db: ${BUILD_DIR}/segbits_gtx_channelx.rdb
${XRAY_DBFIXUP} --db-root ${BUILD_DIR} --zero-db bits.dbf \
--seg-fn-in ${BUILD_DIR}/segbits_gtx_channelx.rdb \
--seg-fn-out ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MASKMERGE} ${BUILD_DIR}/mask_gtx_channelx.db $$(find $(SPECIMENS) -name "segdata_gtx_channel_[0123]*")
pushdb:
mkdir -p $(CELLS_DATA_DIR)
cp attrs.json $(CELLS_DATA_DIR)/gtxe2_channel_attrs.json
cp $(BUILD_DIR)/gtxe2_channel_ports.json $(CELLS_DATA_DIR)/gtxe2_channel_ports.json
BUILD_DIR=$(BUILD_DIR) source pushdb.sh
.PHONY: database pushdb

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fuzzers/064-gtx-channel-conf/attrs.json Normal file
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147
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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
from enum import Enum
from prjxray.segmaker import Segmaker, add_site_group_zero
INT = "INT"
BIN = "BIN"
BOOL = "BOOL"
STR = "STR"
def bitfilter_gtx_channel_x(frame, bit):
# Filter out interconnect bits.
# if frame not in [28, 29, 30, 31]:
# return False
return True
def bitfilter_gtx_channel_x_mid(frame, bit):
# Filter out interconnect bits.
#if frame not in [0, 1, 2, 3]:
# return False
return True
def main():
segmk = Segmaker("design.bits")
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
attrs = json.load(attr_file)
print("Loading tags")
with open("params.json") as f:
primitives_list = json.load(f)
for primitive in primitives_list:
tile_type = primitive["tile_type"]
params_list = primitive["params"]
for params in params_list:
site = params["site"]
if "GTXE2_CHANNEL" not in site:
continue
in_use = params["IN_USE"]
segmk.add_site_tag(site, "IN_USE", in_use)
if in_use:
for param, param_info in attrs.items():
value = params[param]
param_type = param_info["type"]
param_digits = param_info["digits"]
param_values = param_info["values"]
if param_type == INT:
param_encodings = param_info["encoding"]
param_encoding = param_encodings[param_values.index(
value)]
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=param_encoding, digits=param_digits)
[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(
site, '%s[%u]' % (param, i), bitstr[i])
elif param_type == BIN:
bitstr = [
int(x) for x in "{value:0{digits}b}".format(
value=value, digits=param_digits)[::-1]
]
for i in range(param_digits):
segmk.add_site_tag(
site, "%s[%u]" % (param, i), bitstr[i])
elif param_type == BOOL:
segmk.add_site_tag(site, param, value == "TRUE")
else:
assert param_type == STR
# The RXSLIDE_MODE parameter has overlapping bits
# for its possible values. We need to treat it
# differently
if param == "RXSLIDE_MODE":
add_site_group_zero(
segmk, site, "{}.".format(param), param_values,
"OFF", value)
else:
for param_value in param_values:
segmk.add_site_tag(
site, "{}.{}".format(param, param_value),
value == param_value)
for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"RXUSRCLK", "RXUSRCLK2", "DRPCLK"]:
segmk.add_site_tag(site, "INV_" + param, params[param])
gtx_channel_x = [
"GTX_CHANNEL_0",
"GTX_CHANNEL_1",
"GTX_CHANNEL_2",
"GTX_CHANNEL_3",
]
gtx_channel_x_mid = [
"GTX_CHANNEL_0_MID_LEFT",
"GTX_CHANNEL_1_MID_LEFT",
"GTX_CHANNEL_2_MID_LEFT",
"GTX_CHANNEL_3_MID_LEFT",
"GTX_CHANNEL_0_MID_RIGHT",
"GTX_CHANNEL_1_MID_RIGHT",
"GTX_CHANNEL_2_MID_RIGHT",
"GTX_CHANNEL_3_MID_RIGHT",
]
if tile_type in gtx_channel_x:
bitfilter = bitfilter_gtx_channel_x
elif tile_type in gtx_channel_x_mid:
bitfilter = bitfilter_gtx_channel_x_mid
else:
assert False, tile_type
segmk.compile(bitfilter=bitfilter)
segmk.write()
if __name__ == '__main__':
main()

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fuzzers/064-gtx-channel-conf/generate.tcl Normal file
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# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-1619}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-17}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-18}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-19}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-19}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-20}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-20}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-21}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-22}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
set_property IS_ENABLED 0 [get_drc_checks {AVAL-23}]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

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fuzzers/064-gtx-channel-conf/generate_ports.tcl Normal file
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# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
create_project -force -name design -part $::env(XRAY_PART)
set_property design_mode PinPlanning [current_fileset]
open_io_design -name io_1
dump_pins $::env(FILE_NAME) GTXE2_CHANNEL

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fuzzers/064-gtx-channel-conf/pushdb.sh Normal file
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#!/bin/bash
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
if ! test $(find ${BUILD_DIR} -name "segdata_gtx_channel_[0123]_mid_*.txt" | wc -c) -eq 0
then
${XRAY_MERGEDB} gtx_channel_0_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_1_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_2_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_3_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_0_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_1_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_2_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_3_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_0_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_1_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_2_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_3_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_0_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_1_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_2_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_3_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
fi
if ! test $(find ${BUILD_DIR} -name "segdata_gtx_channel_[0123].txt" | wc -c) -eq 0
then
${XRAY_MERGEDB} gtx_channel_0 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_1 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_2 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} gtx_channel_3 ${BUILD_DIR}/segbits_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_0 ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_1 ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_2 ${BUILD_DIR}/mask_gtx_channelx.db
${XRAY_MERGEDB} mask_gtx_channel_3 ${BUILD_DIR}/mask_gtx_channelx.db
fi

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import os
import random
from collections import namedtuple
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import verilog
from prjxray.lut_maker import LutMaker
from prjxray.db import Database
INT = "INT"
BIN = "BIN"
BOOL = "BOOL"
STR = "STR"
def gen_sites(site):
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
already_used = list()
for tile_name in sorted(grid.tiles()):
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
if gridinfo.tile_type not in [
"GTX_CHANNEL_0",
"GTX_CHANNEL_1",
"GTX_CHANNEL_2",
"GTX_CHANNEL_3",
"GTX_CHANNEL_0_MID_LEFT",
"GTX_CHANNEL_1_MID_LEFT",
"GTX_CHANNEL_2_MID_LEFT",
"GTX_CHANNEL_3_MID_LEFT",
"GTX_CHANNEL_0_MID_RIGHT",
"GTX_CHANNEL_1_MID_RIGHT",
"GTX_CHANNEL_2_MID_RIGHT",
"GTX_CHANNEL_3_MID_RIGHT",
] or gridinfo.tile_type in already_used:
continue
else:
tile_type = gridinfo.tile_type
already_used.append(tile_type)
for site_name, site_type in gridinfo.sites.items():
if site_type != site:
continue
if "RIGHT" in tile_type and "X0" in site_name:
continue
if "LEFT" in tile_type and "X1" in site_name:
continue
yield tile_name, tile_type, site_name, site_type
def main():
print(
'''
module top(
input wire in,
output wire out
);
assign out = in;
''')
luts = LutMaker()
primitives_list = list()
for tile_name, tile_type, site_name, site_type in gen_sites(
"GTXE2_CHANNEL"):
params_list = list()
params_dict = dict()
params_dict["tile_type"] = tile_type
params = dict()
params['site'] = site_name
verilog_attr = ""
verilog_attr = "#("
fuz_dir = os.getenv("FUZDIR", None)
assert fuz_dir
with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
attrs = json.load(attrs_file)
in_use = bool(random.randint(0, 9))
params["IN_USE"] = in_use
if in_use:
for param, param_info in attrs.items():
param_type = param_info["type"]
param_values = param_info["values"]
param_digits = param_info["digits"]
if param_type == INT:
value = random.choice(param_values)
value_str = value
elif param_type == BIN:
value = random.randint(0, param_values[0])
value_str = "{digits}'b{value:0{digits}b}".format(
value=value, digits=param_digits)
elif param_type in [BOOL, STR]:
value = random.choice(param_values)
value_str = verilog.quote(value)
params[param] = value
verilog_attr += """
.{}({}),""".format(param, value_str)
verilog_ports = ""
for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
"RXUSRCLK", "RXUSRCLK2", "DRPCLK"]:
is_inverted = random.randint(0, 1)
params[param] = is_inverted
verilog_attr += """
.IS_{}_INVERTED({}),""".format(param, is_inverted)
verilog_ports += """
.{}({}),""".format(param, luts.get_next_output_net())
verilog_attr = verilog_attr.rstrip(",")
verilog_attr += "\n)"
print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
print(
"""GTXE2_CHANNEL {attrs} {site} (
{ports}
);
""".format(
attrs=verilog_attr,
site=tile_type.lower(),
ports=verilog_ports.rstrip(",")))
params_list.append(params)
params_dict["params"] = params_list
primitives_list.append(params_dict)
for l in luts.create_wires_and_luts():
print(l)
print("endmodule")
with open('params.json', 'w') as f:
json.dump(primitives_list, f, indent=2)
if __name__ == '__main__':
main()