clbncy0 fuzzer

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>

fuzzers/013-clbncy0/.gitignore

@@ -0,0 +1,2 @@
+/specimen_*/
+/*.segbits

fuzzers/013-clbncy0/Makefile

@@ -0,0 +1,22 @@
+N := 1
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+database: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
+
+pushdb:
+	${XRAY_MERGEDB} clbll_l seg_clblx.segbits
+	${XRAY_MERGEDB} clbll_r seg_clblx.segbits
+	${XRAY_MERGEDB} clblm_l seg_clblx.segbits
+	${XRAY_MERGEDB} clblm_r seg_clblx.segbits
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+
+.PHONY: database pushdb clean
+

fuzzers/013-clbncy0/README.txt

@@ -0,0 +1,8 @@
+Purpose:
+Document ACY0 family of CLB muxes
+
+Algorithm:
+
+Outcome:
+
+

fuzzers/013-clbncy0/generate.py

@@ -0,0 +1,29 @@
+#!/usr/bin/env python3
+
+import sys, re
+
+sys.path.append("../../../utils/")
+from segmaker import segmaker
+
+segmk = segmaker("design.bits")
+
+print("Loading tags")
+'''
+module,loc,bel,n
+clb_NCY0_MX,SLICE_X12Y100,A6LUT,3
+clb_NCY0_O5,SLICE_X16Y100,C6LUT,0
+clb_NCY0_O5,SLICE_X17Y100,A6LUT,2
+'''
+f = open('params.csv', 'r')
+f.readline()
+for l in f:
+    module,loc,bel,n = l.split(',')
+    n = int(n)
+    # A, B, etc
+    which = bel[0]
+
+    # One bit, set on O5
+    segmk.addtag(loc, "CARRY4.%cCY0" % which, module == 'clb_NCY0_O5')
+segmk.compile()
+segmk.write()
+

fuzzers/013-clbncy0/generate.sh

@@ -0,0 +1,18 @@
+#!/bin/bash
+
+set -ex
+
+. ../../utils/genheader.sh
+
+#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
+
+python3 ../top.py >top.v
+vivado -mode batch -source ../generate.tcl
+test -z $(fgrep CRITICAL vivado.log)
+
+for x in design*.bit; do
+	../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
+done
+
+python3 ../generate.py
+

fuzzers/013-clbncy0/generate.tcl

@@ -0,0 +1,26 @@
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+create_pblock roi
+set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+

fuzzers/013-clbncy0/top.py

@@ -0,0 +1,153 @@
+import random
+
+random.seed(0)
+
+CLBN = 400
+# SLICE_X12Y100
+# SLICE_X27Y149
+SLICEX = (12, 28)
+SLICEY = (100, 150)
+# 800
+SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
+print('//SLICEX: %s' % str(SLICEX))
+print('//SLICEY: %s' % str(SLICEY))
+print('//SLICEN: %s' % str(SLICEN))
+print('//Requested CLBs: %s' % str(CLBN))
+
+def gen_slices():
+    for slicey in range(*SLICEY):
+        for slicex in range(*SLICEX):
+            yield "SLICE_X%dY%d" % (slicex, slicey)
+
+DIN_N = CLBN * 8
+DOUT_N = CLBN * 8
+
+lut_bels = ['A6LUT', 'B6LUT', 'C6LUT', 'D6LUT']
+
+print('''
+module top(input clk, stb, di, output do);
+    localparam integer DIN_N = %d;
+    localparam integer DOUT_N = %d;
+
+    reg [DIN_N-1:0] din;
+    wire [DOUT_N-1:0] dout;
+
+    reg [DIN_N-1:0] din_shr;
+    reg [DOUT_N-1:0] dout_shr;
+
+    always @(posedge clk) begin
+        din_shr <= {din_shr, di};
+        dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+        if (stb) begin
+            din <= din_shr;
+            dout_shr <= dout;
+        end
+    end
+
+    assign do = dout_shr[DOUT_N-1];
+
+    roi roi (
+        .clk(clk),
+        .din(din),
+        .dout(dout)
+    );
+endmodule
+''' % (DIN_N, DOUT_N))
+
+f = open('params.csv', 'w')
+f.write('module,loc,bel,n\n')
+slices = gen_slices()
+print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
+for i in range(CLBN):
+    bel = ''
+
+    if random.randint(0, 1):
+        module = 'clb_NCY0_MX'
+    else:
+        module = 'clb_NCY0_O5'
+    n = random.randint(0, 3)
+    loc = next(slices)
+    bel = lut_bels[n]
+
+    print('    %s' % module)
+    print('            #(.LOC("%s"), .BEL("%s"), .N(%d))' % (loc, bel, n))
+    print('            clb_%d (.clk(clk), .din(din[  %d +: 8]), .dout(dout[  %d +: 8]));' % (i, 8 * i, 8 * i))
+
+    f.write('%s,%s,%s,%s\n' % (module, loc, bel, n))
+f.close()
+print('''endmodule
+
+// ---------------------------------------------------------------------
+
+''')
+
+print('''
+module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC="SLICE_X16Y129_FIXME";
+    parameter BEL="A6LUT_FIXME";
+    parameter N=-1;
+
+    wire [3:0] o;
+    assign dout[0] = o[1];
+    wire o6, o5;
+    reg [3:0] s;
+
+    always @(*) begin
+        s = din[7:4];
+        s[N] = o6;
+    end
+
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LUT6_2 #(
+		.INIT(64'h8000_0000_0000_0001)
+	) lut (
+		.I0(din[0]),
+		.I1(din[1]),
+		.I2(din[2]),
+		.I3(din[3]),
+		.I4(din[4]),
+		.I5(din[5]),
+		.O5(o5),
+		.O6(o6));
+
+	(* LOC=LOC, KEEP, DONT_TOUCH *)
+    CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
+endmodule
+
+module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC="SLICE_X16Y129_FIXME";
+    parameter BEL="A6LUT_FIXME";
+    parameter N=-1;
+
+    wire [3:0] o;
+    assign dout[0] = o[1];
+    wire o6, o5;
+    reg [3:0] s;
+    reg [3:0] di;
+
+    always @(*) begin
+        s = din[7:4];
+        s[N] = o6;
+        
+        di = {din[3:0]};
+        di[N] = o5;
+    end
+
+	(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
+	LUT6_2 #(
+		.INIT(64'h8000_0000_0000_0001)
+	) lut (
+		.I0(din[0]),
+		.I1(din[1]),
+		.I2(din[2]),
+		.I3(din[3]),
+		.I4(din[4]),
+		.I5(din[5]),
+		.O5(o5),
+		.O6(o6));
+
+	(* LOC=LOC, KEEP, DONT_TOUCH *)
+    CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
+endmodule
+''')
+

minitests/clb_ncy0/top.v

@@ -28,24 +28,24 @@ endmodule
 
 module roi(input clk, input [255:0] din, output [255:0] dout);
     clb_NCY0_MX # (.LOC("SLICE_X20Y100"), .BEL("A6LUT"), .N(0))
-    am (.clk(clk), .din(din[  0 +: 8]), .dout(dout[0 +: 8]));
+            am (.clk(clk), .din(din[  0 +: 8]), .dout(dout[0 +: 8]));
     clb_NCY0_O5 # (.LOC("SLICE_X20Y101"), .BEL("A6LUT"), .N(0))
-    a5 (.clk(clk), .din(din[  8 +: 8]), .dout(dout[8 +: 8]));
+            a5 (.clk(clk), .din(din[  8 +: 8]), .dout(dout[8 +: 8]));
 
     clb_NCY0_MX # (.LOC("SLICE_X20Y102"), .BEL("B6LUT"), .N(1))
-    bm (.clk(clk), .din(din[  16 +: 8]), .dout(dout[16 +: 8]));
+            bm (.clk(clk), .din(din[  16 +: 8]), .dout(dout[16 +: 8]));
     clb_NCY0_O5 # (.LOC("SLICE_X20Y103"), .BEL("B6LUT"), .N(1))
-    b5 (.clk(clk), .din(din[  24 +: 8]), .dout(dout[24 +: 8]));
+            b5 (.clk(clk), .din(din[  24 +: 8]), .dout(dout[24 +: 8]));
 
     clb_NCY0_MX # (.LOC("SLICE_X20Y104"), .BEL("C6LUT"), .N(2))
-    cm (.clk(clk), .din(din[  32 +: 8]), .dout(dout[32 +: 8]));
+            cm (.clk(clk), .din(din[  32 +: 8]), .dout(dout[32 +: 8]));
     clb_NCY0_O5 # (.LOC("SLICE_X20Y105"), .BEL("C6LUT"), .N(2))
-    c5 (.clk(clk), .din(din[  40 +: 8]), .dout(dout[40 +: 8]));
+            c5 (.clk(clk), .din(din[  40 +: 8]), .dout(dout[40 +: 8]));
 
     clb_NCY0_MX # (.LOC("SLICE_X20Y106"), .BEL("D6LUT"), .N(3))
-    dm (.clk(clk), .din(din[  48 +: 8]), .dout(dout[48 +: 8]));
+            dm (.clk(clk), .din(din[  48 +: 8]), .dout(dout[48 +: 8]));
     clb_NCY0_O5 # (.LOC("SLICE_X20Y107"), .BEL("D6LUT"), .N(3))
-    d5 (.clk(clk), .din(din[  56 +: 8]), .dout(dout[56 +: 8]));
+            d5 (.clk(clk), .din(din[  56 +: 8]), .dout(dout[56 +: 8]));
 endmodule
 
 module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);