mirror of https://github.com/openXC7/prjxray.git
clbncy0 fuzzer
Signed-off-by: John McMaster <JohnDMcMaster@gmail.com> Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster
Tim 'mithro' Ansell
parent
6f3f93d81b
commit
e52d9cb59a
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/specimen_*/
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/*.segbits
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N := 1
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SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
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SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
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database: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
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pushdb:
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${XRAY_MERGEDB} clbll_l seg_clblx.segbits
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${XRAY_MERGEDB} clbll_r seg_clblx.segbits
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${XRAY_MERGEDB} clblm_l seg_clblx.segbits
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${XRAY_MERGEDB} clblm_r seg_clblx.segbits
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$(SPECIMENS_OK):
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bash generate.sh $(subst /OK,,$@)
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touch $@
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
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.PHONY: database pushdb clean
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@ -0,0 +1,8 @@
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Purpose:
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Document ACY0 family of CLB muxes
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Algorithm:
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Outcome:
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#!/usr/bin/env python3
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import sys, re
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sys.path.append("../../../utils/")
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from segmaker import segmaker
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segmk = segmaker("design.bits")
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print("Loading tags")
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'''
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module,loc,bel,n
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clb_NCY0_MX,SLICE_X12Y100,A6LUT,3
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clb_NCY0_O5,SLICE_X16Y100,C6LUT,0
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clb_NCY0_O5,SLICE_X17Y100,A6LUT,2
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'''
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f = open('params.csv', 'r')
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f.readline()
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for l in f:
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module,loc,bel,n = l.split(',')
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n = int(n)
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# A, B, etc
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which = bel[0]
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# One bit, set on O5
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segmk.addtag(loc, "CARRY4.%cCY0" % which, module == 'clb_NCY0_O5')
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segmk.compile()
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segmk.write()
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#!/bin/bash
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set -ex
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. ../../utils/genheader.sh
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#echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh
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python3 ../top.py >top.v
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vivado -mode batch -source ../generate.tcl
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test -z $(fgrep CRITICAL vivado.log)
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for x in design*.bit; do
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../../../build/tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -z -y $x
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done
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python3 ../generate.py
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
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set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,153 @@
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import random
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random.seed(0)
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CLBN = 400
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# SLICE_X12Y100
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# SLICE_X27Y149
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SLICEX = (12, 28)
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SLICEY = (100, 150)
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# 800
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SLICEN = (SLICEY[1] - SLICEY[0]) * (SLICEX[1] - SLICEX[0])
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print('//SLICEX: %s' % str(SLICEX))
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print('//SLICEY: %s' % str(SLICEY))
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print('//SLICEN: %s' % str(SLICEN))
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print('//Requested CLBs: %s' % str(CLBN))
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def gen_slices():
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for slicey in range(*SLICEY):
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for slicex in range(*SLICEX):
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yield "SLICE_X%dY%d" % (slicex, slicey)
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DIN_N = CLBN * 8
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DOUT_N = CLBN * 8
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lut_bels = ['A6LUT', 'B6LUT', 'C6LUT', 'D6LUT']
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print('''
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module top(input clk, stb, di, output do);
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localparam integer DIN_N = %d;
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localparam integer DOUT_N = %d;
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reg [DIN_N-1:0] din;
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wire [DOUT_N-1:0] dout;
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reg [DIN_N-1:0] din_shr;
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reg [DOUT_N-1:0] dout_shr;
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always @(posedge clk) begin
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din_shr <= {din_shr, di};
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dout_shr <= {dout_shr, din_shr[DIN_N-1]};
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if (stb) begin
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din <= din_shr;
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dout_shr <= dout;
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end
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end
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assign do = dout_shr[DOUT_N-1];
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roi roi (
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.clk(clk),
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.din(din),
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.dout(dout)
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);
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endmodule
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''' % (DIN_N, DOUT_N))
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f = open('params.csv', 'w')
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f.write('module,loc,bel,n\n')
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slices = gen_slices()
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print('module roi(input clk, input [%d:0] din, output [%d:0] dout);' % (DIN_N - 1, DOUT_N - 1))
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for i in range(CLBN):
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bel = ''
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if random.randint(0, 1):
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module = 'clb_NCY0_MX'
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else:
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module = 'clb_NCY0_O5'
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n = random.randint(0, 3)
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loc = next(slices)
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bel = lut_bels[n]
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print(' %s' % module)
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print(' #(.LOC("%s"), .BEL("%s"), .N(%d))' % (loc, bel, n))
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print(' clb_%d (.clk(clk), .din(din[ %d +: 8]), .dout(dout[ %d +: 8]));' % (i, 8 * i, 8 * i))
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f.write('%s,%s,%s,%s\n' % (module, loc, bel, n))
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f.close()
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print('''endmodule
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// ---------------------------------------------------------------------
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''')
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print('''
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module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X16Y129_FIXME";
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parameter BEL="A6LUT_FIXME";
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parameter N=-1;
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wire [3:0] o;
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assign dout[0] = o[1];
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wire o6, o5;
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reg [3:0] s;
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always @(*) begin
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s = din[7:4];
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s[N] = o6;
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end
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(din[3:0]), .S(s), .CYINIT(1'b0), .CI());
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endmodule
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module clb_NCY0_O5 (input clk, input [7:0] din, output [7:0] dout);
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parameter LOC="SLICE_X16Y129_FIXME";
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parameter BEL="A6LUT_FIXME";
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parameter N=-1;
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wire [3:0] o;
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assign dout[0] = o[1];
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wire o6, o5;
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reg [3:0] s;
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reg [3:0] di;
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always @(*) begin
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s = din[7:4];
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s[N] = o6;
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di = {din[3:0]};
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di[N] = o5;
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end
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(* LOC=LOC, BEL=BEL, KEEP, DONT_TOUCH *)
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LUT6_2 #(
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.INIT(64'h8000_0000_0000_0001)
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) lut (
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.I0(din[0]),
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.I1(din[1]),
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.I2(din[2]),
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.I3(din[3]),
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.I4(din[4]),
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.I5(din[5]),
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.O5(o5),
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.O6(o6));
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(* LOC=LOC, KEEP, DONT_TOUCH *)
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CARRY4 carry4(.O(o), .CO(), .DI(di), .S(s), .CYINIT(1'b0), .CI());
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endmodule
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''')
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@ -28,24 +28,24 @@ endmodule
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module roi(input clk, input [255:0] din, output [255:0] dout);
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clb_NCY0_MX # (.LOC("SLICE_X20Y100"), .BEL("A6LUT"), .N(0))
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am (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
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am (.clk(clk), .din(din[ 0 +: 8]), .dout(dout[0 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y101"), .BEL("A6LUT"), .N(0))
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a5 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
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a5 (.clk(clk), .din(din[ 8 +: 8]), .dout(dout[8 +: 8]));
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clb_NCY0_MX # (.LOC("SLICE_X20Y102"), .BEL("B6LUT"), .N(1))
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bm (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
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bm (.clk(clk), .din(din[ 16 +: 8]), .dout(dout[16 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y103"), .BEL("B6LUT"), .N(1))
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b5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
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b5 (.clk(clk), .din(din[ 24 +: 8]), .dout(dout[24 +: 8]));
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clb_NCY0_MX # (.LOC("SLICE_X20Y104"), .BEL("C6LUT"), .N(2))
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cm (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[32 +: 8]));
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cm (.clk(clk), .din(din[ 32 +: 8]), .dout(dout[32 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y105"), .BEL("C6LUT"), .N(2))
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c5 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[40 +: 8]));
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c5 (.clk(clk), .din(din[ 40 +: 8]), .dout(dout[40 +: 8]));
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clb_NCY0_MX # (.LOC("SLICE_X20Y106"), .BEL("D6LUT"), .N(3))
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dm (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[48 +: 8]));
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dm (.clk(clk), .din(din[ 48 +: 8]), .dout(dout[48 +: 8]));
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clb_NCY0_O5 # (.LOC("SLICE_X20Y107"), .BEL("D6LUT"), .N(3))
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d5 (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[56 +: 8]));
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d5 (.clk(clk), .din(din[ 56 +: 8]), .dout(dout[56 +: 8]));
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endmodule
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module clb_NCY0_MX (input clk, input [7:0] din, output [7:0] dout);
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