mirror of https://github.com/openXC7/prjxray.git
roi_harness: I/O partial reconfiguration test harness
Signed-off-by: John McMaster <johndmcmaster@gmail.com>
This commit is contained in:
John McMaster
parent
5a155de8bc
commit
e148d2ac14
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/.Xil
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/design/
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/design.bit
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/design.bits
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/design.dcp
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/usage_statistics_webtalk.*
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/vivado*
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/design.txt
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all:
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bash runme.sh
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clean:
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rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
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.PHONY: all clean
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Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness
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Basic idea:
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-LOC LUTs in the ROI to terminate input and output routing
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-Let Vivado LOC the rest of the logic
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-Manually route signals in and out of the ROI enough to avoid routing loops into the ROI
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-Let Vivado finish the rest of the routes
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There is no logic outside of the ROI in order to keep IOB to ROI delays short
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Its expected the end user will rip out everything inside the ROI
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To target Arty A7 you should source the artix DB environment script then source arty.sh
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export XRAY_PART=xc7a35tcsg324-1
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#!/bin/bash
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set -ex
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vivado -mode batch -source runme.tcl
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test -z "$(fgrep CRITICAL vivado.log)"
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# WARNING: this is somewhat paramaterized, but is only tested on A50T/A35T with the traditional ROI
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# Your ROI should at least have a SLICEL on the left
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set DIN_N 8
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set DOUT_N 8
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# X12 in the ROI, X10 just to the left
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# Start at bottom left of ROI and work up
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# (IOs are to left)
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# SLICE_X12Y100:SLICE_X27Y149
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# set X_BASE 12
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set X_BASE [lindex [split [lindex [split "$::env(XRAY_ROI)" Y] 0] X] 1]
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set Y_BASE [lindex [split [lindex [split "$::env(XRAY_ROI)" Y] 1] :] 0]
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# set Y_DIN_BASE 100
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set Y_CLK_BASE $Y_BASE
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# Clock lut in middle
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set Y_DIN_BASE [expr "$Y_CLK_BASE + 1"]
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set Y_DOUT_BASE [expr "$Y_DIN_BASE + $DIN_N"]
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puts "Environment"
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puts " XRAY_ROI: $::env(XRAY_ROI)"
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puts " X_BASE: $X_BASE"
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puts " Y_DIN_BASE: $Y_DIN_BASE"
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puts " Y_CLK_BASE: $Y_CLK_BASE"
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puts " Y_DOUT_BASE: $Y_DOUT_BASE"
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source ../../utils/utils.tcl
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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# added flatten_hierarchy
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# dout_shr was getting folded into the pblock
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# synth_design -top top -flatten_hierarchy none -no_lc -keep_equivalent_registers -resource_sharing off
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synth_design -top top -flatten_hierarchy none -verilog_define DIN_N=$DIN_N -verilog_define DOUT_N=$DOUT_N
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# TODO: find a way to more automatically assign these?
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# Sequential I/O Bank 16 layout
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set part "$::env(XRAY_PART)"
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if {$part eq "xc7a50tfgg484-1"} {
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# Partial list, expand as needed
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set bank_16 "F21 G22 G21 D21 E21 D22 E22 A21 B21 B22 C22 C20 D20 F20 F19 A19 A18"
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set banki 0
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# CLK
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set pin [lindex $bank_16 $banki]
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incr banki
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "clk"]
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# DIN
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for {set j 0} {$j < $DIN_N} {incr j} {
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set pin [lindex $bank_16 $banki]
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incr banki
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "din[$j]"]
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}
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# DOUT
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for {set j 0} {$j < $DOUT_N} {incr j} {
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set pin [lindex $bank_16 $banki]
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incr banki
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "dout[$j]"]
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}
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# Arty A7 optimized I/O layout
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} elseif {$part eq "xc7a35tcsg324-1"} {
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# https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
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set pmod_ja "G13 B11 A11 D12 D13 B18 A18 K16"
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set pmod_jb "E15 E16 D15 C15 J17 J18 K15 J15"
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set pmod_jc "U12 V12 V10 V11 U14 V14 T13 U13"
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# CLK on Pmod JA
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set pin [lindex $pmod_ja 0]
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set_property -dict "PACKAGE_PIN G13 IOSTANDARD LVCMOS33" [get_ports "clk"]
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# DIN on Pmod JB
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for {set i 0} {$i < $DIN_N} {incr i} {
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set pin [lindex $pmod_jb $i]
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "din[$i]"]
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}
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# DOUT on Pmod JC
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for {set i 0} {$i < $DOUT_N} {incr i} {
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set pin [lindex $pmod_jc $i]
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set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "dout[$i]"]
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}
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} else {
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error "Unsupported part $part"
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}
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create_pblock roi
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set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
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add_cells_to_pblock [get_pblocks roi] [get_cells roi]
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resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
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#write_checkpoint -force synth.dcp
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proc loc_roi_clk_left {ff_x ff_y} {
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# Place an ROI clk on the left edge of the ROI
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# It doesn't actually matter where we place this, just do it to keep things neat looking
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# ff_x: ROI SLICE X position
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# ff_yy: row primitives will be placed at
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set slice_ff "SLICE_X${ff_x}Y${ff_y}"
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# Fix FFs to guide route in
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set cell [get_cells "roi/clk_reg_reg"]
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set_property LOC $slice_ff $cell
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set_property BEL AFF $cell
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}
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proc loc_roi_in_left {index lut_x y} {
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# Place an ROI input on the left edge of the ROI
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# index: input bus index
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# lut_x: ROI SLICE X position. FF position is implicit to left
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# y: row primitives will be placed at
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set slice_lut "SLICE_X${lut_x}Y${y}"
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# Fix LUTs near the edge
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set cell [get_cells "roi/ins[$index].lut"]
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set_property LOC $slice_lut $cell
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set_property BEL A6LUT $cell
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}
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proc loc_roi_out_left {index lut_x y} {
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# Place an ROI output on the left edge of the ROI
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# index: input bus index
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# lut_x: ROI SLICE X position. FF position is implicit to left
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# y: row primitives will be placed at
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set slice_lut "SLICE_X${lut_x}Y${y}"
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# Fix LUTs near the edge
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set cell [get_cells "roi/outs[$index].lut"]
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set_property LOC $slice_lut $cell
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set_property BEL A6LUT $cell
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}
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if {1} {
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set x $X_BASE
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# Place ROI clock right after inputs
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puts "Placing ROI clock"
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loc_roi_clk_left $x $Y_CLK_BASE
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# Place ROI inputs
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puts "Placing ROI inputs"
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set y $Y_DIN_BASE
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for {set i 0} {$i < $DIN_N} {incr i} {
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loc_roi_in_left $i $x $y
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set y [expr {$y + 1}]
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}
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# Place ROI outputs
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set y $Y_DOUT_BASE
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puts "Placing ROI outputs"
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for {set i 0} {$i < $DOUT_N} {incr i} {
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loc_roi_out_left $i $x $y
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set y [expr {$y + 1}]
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}
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}
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place_design
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#write_checkpoint -force placed.dcp
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# Version with more error checking for missing end node
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# Will do best effort in this case
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proc route_via2 {net nodes} {
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# net: net as string
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# nodes: string list of one or more intermediate routing nodes to visit
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set net [get_nets $net]
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# Start at the net source
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set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
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# End at the net destination
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# For sone reason this doesn't always show up
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set site_pins [get_site_pins -filter {DIRECTION == IN} -of_objects $net]
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if {$site_pins eq ""} {
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puts "WARNING: could not find end node"
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#error "Could not find end node"
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} else {
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set end_node [get_nodes -of_objects]
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lappend nodes [$end_node]
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}
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puts ""
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puts "Routing net $net:"
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foreach to_node $nodes {
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if {$to_node eq ""} {
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error "Empty node"
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}
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# Node string to object
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set to_node [get_nodes -of_objects [get_wires $to_node]]
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# Start at last routed position
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set from_node [lindex $fixed_route end]
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# Let vivado do heavy liftin in between
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set route [find_routing_path -quiet -from $from_node -to $to_node]
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if {$route == ""} {
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# Some errors print a huge route
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puts [concat [string range " $from_node -> $to_node" 0 1000] ": no route found - assuming direct PIP"]
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lappend fixed_route $to_node
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} {
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puts [concat [string range " $from_node -> $to_node: $route" 0 1000] "routed"]
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set fixed_route [concat $fixed_route [lrange $route 1 end]]
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}
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set_property -quiet FIXED_ROUTE $fixed_route $net
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}
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set_property -quiet FIXED_ROUTE $fixed_route $net
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puts ""
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}
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# XXX: maybe add IOB?
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set fp [open "design.txt" w]
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puts $fp "name node"
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if {1} {
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set x $X_BASE
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# Nothing needed for clk
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# It will go to high level interconnect that goes everywhere
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puts "Routing ROI inputs"
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# Arbitrary offset as observed
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set y [expr {$Y_DIN_BASE - 1}]
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for {set i 0} {$i < $DIN_N} {incr i} {
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#route_via2 "din_IBUF[$i]" "INT_R_X9Y${y}/NE2BEG3"
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# needed to force routes away to avoid looping into ROI
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#set x_EE2BEG3 [expr {$x - 2}]
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set x_EE2BEG3 7
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set x_NE2BEG3 9
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set node "INT_R_X${x_NE2BEG3}Y${y}/NE2BEG3"
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route_via2 "din_IBUF[$i]" "INT_R_X${x_EE2BEG3}Y${y}/EE2BEG3 $node"
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puts $fp "din[$i] $node"
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set y [expr {$y + 1}]
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}
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puts "Routing ROI outputs"
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# Arbitrary offset as observed
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set y [expr {$Y_DOUT_BASE + 0}]
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for {set i 0} {$i < $DOUT_N} {incr i} {
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# XXX: find a better solution if we need harness long term
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# works on 50t but not 35t
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if {$part eq "xc7a50tfgg484-1"} {
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set node "INT_L_X10Y${y}/WW2BEG0"
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route_via2 "roi/dout[$i]" "$node"
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# works on 35t but not 50t
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} elseif {$part eq "xc7a35tcsg324-1"} {
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set node "INT_L_X10Y${y}/SW6BEG0"
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route_via2 "roi/dout[$i]" "$node"
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} else {
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error "Unsupported part $part"
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}
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puts $fp "dout[$i] $node"
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set y [expr {$y + 1}]
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}
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}
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close $fp
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puts "routing design"
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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@ -0,0 +1,65 @@
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//See README and tcl for more info
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`ifndef DIN_N
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`define DIN_N 4
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`endif
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`ifndef DOUT_N
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`define DOUT_N 4
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`endif
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module top(input wire clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = `DIN_N;
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parameter DOUT_N = `DOUT_N;
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roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N)) roi (
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.clk(clk),
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.din(din), .dout(dout));
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endmodule
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module roi(input clk,
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input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
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parameter DIN_N = 4;
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parameter DOUT_N = 4;
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genvar i;
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generate
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//CLK
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(* KEEP, DONT_TOUCH *)
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reg clk_reg;
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always @(posedge clk) begin
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clk_reg <= clk_reg;
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end
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//DIN
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for (i = 0; i < DIN_N; i = i+1) begin:ins
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(din[i]),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O());
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end
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//DOUT
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for (i = 0; i < DOUT_N; i = i+1) begin:outs
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(* KEEP, DONT_TOUCH *)
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LUT6 #(
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.INIT(64'b01)
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) lut (
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.I0(1'b0),
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.I1(1'b0),
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.I2(1'b0),
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.I3(1'b0),
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.I4(1'b0),
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.I5(1'b0),
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.O(dout[i]));
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end
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endgenerate
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endmodule
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