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picorv y and v tests 

Signed-off-by: John McMaster <JohnDMcMaster@gmail.com>
Signed-off-by: Tim 'mithro' Ansell <mithro@mithis.com>
This commit is contained in:
John McMaster 2017-12-07 10:33:20 -08:00 committed by Tim 'mithro' Ansell
parent e90eedd2c7
commit df26f1f2d3
15 changed files with 6286 additions and 0 deletions
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minitests/picorv32-v/.gitignore vendored Normal file
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/.Xil
/design/
/design.bit
/design.bits
/design.dcp
/usage_statistics_webtalk.*
/vivado*
/design.txt

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N := 3
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
all:
bash runme.sh
clean:
rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
.PHONY: database pushdb clean

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Unknown bits CPU synthesis test (Vivado synthesis)

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#!/bin/bash
set -ex
# rm -f vivado*.log vivado*.jou
vivado -mode batch -source runme.tcl
test -z $(fgrep CRITICAL vivado.log)
${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
${XRAY_SEGPRINT} -z -D design.bits >design.txt
# test -z $(cat design.txt)
test $(wc -c design.txt |cut -d\ -f 1) = 0

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create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
read_verilog picorv32.v
synth_design -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
create_pblock roi
set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

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//move some stuff to minitests/ncy0
`define SEED 32'h12345678
module top(input clk, stb, di, output do);
localparam integer DIN_N = 42;
localparam integer DOUT_N = 79;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N))
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
module roi(input clk, input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
parameter integer DIN_N = -1;
parameter integer DOUT_N = -1;
picorv32 picorv32 (
.clk(clk),
.resetn(din[0]),
.mem_valid(dout[0]),
.mem_instr(dout[1]),
.mem_ready(din[1]),
.mem_addr(dout[33:2]),
.mem_wdata(dout[66:34]),
.mem_wstrb(dout[70:67]),
.mem_rdata(din[33:2])
);
randluts randluts (
.din(din[41:34]),
.dout(dout[78:71])
);
endmodule
module randluts(input [7:0] din, output [7:0] dout);
localparam integer N = 250;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule

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/.Xil
/design/
/design.bit
/design.bits
/design.dcp
/usage_statistics_webtalk.*
/vivado*
/design.txt

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N := 3
SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
all:
bash runme.sh
clean:
rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt *.edif .Xil
.PHONY: database pushdb clean

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Unknown bits CPU synthesis test (Vivado synthesis)

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read_verilog top.v
read_verilog picorv32.v
synth_xilinx -edif top.edif -top top
# read_verilog picorv32.v
# synth_xilinx -edif top.edif -top picorv32

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#!/bin/bash
set -ex
yosys run_yosys.ys
vivado -mode batch -source runme.tcl
test -z $(fgrep CRITICAL vivado.log)
${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
${XRAY_SEGPRINT} -z -D design.bits >design.txt
# test -z $(cat design.txt)
test $(wc -c design.txt |cut -d\ -f 1) = 0

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create_project -force -part $::env(XRAY_PART) design design
# read_verilog top.v
# read_verilog picorv32.v
# synth_design -top top
#read_xdc example.xdc
read_edif top.edif
# link_design -part xc7a35tcpg236-1 -top top
link_design -part $::env(XRAY_PART) -top top
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
create_pblock roi
set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
add_cells_to_pblock [get_pblocks roi] [get_cells roi]
resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit

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//move some stuff to minitests/ncy0
`define SEED 32'h12345678
module top(input clk, stb, di, output do);
localparam integer DIN_N = 42;
localparam integer DOUT_N = 79;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N))
roi (
.clk(clk),
.din(din),
.dout(dout)
);
endmodule
//# ERROR: Assert `range_left >= range_right || (range_left == -1 && range_right == 0)' failed in frontends/ast/genrtlil.cc:861.
//module roi(input clk, input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
module roi(input clk, input [42-1:0] din, output [79-1:0] dout);
parameter integer DIN_N = -1;
parameter integer DOUT_N = -1;
picorv32 picorv32 (
.clk(clk),
.resetn(din[0]),
.mem_valid(dout[0]),
.mem_instr(dout[1]),
.mem_ready(din[1]),
.mem_addr(dout[33:2]),
.mem_wdata(dout[66:34]),
.mem_wstrb(dout[70:67]),
.mem_rdata(din[33:2])
);
randluts randluts (
.din(din[41:34]),
.dout(dout[78:71]));
endmodule
module randluts(input [7:0] din, output [7:0] dout);
//localparam integer N = 250;
localparam integer N = 100;
function [31:0] xorshift32(input [31:0] xorin);
begin
xorshift32 = xorin;
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
function [63:0] lutinit(input [7:0] a, b);
begin
lutinit[63:32] = xorshift32(xorshift32(xorshift32(xorshift32({a, b} ^ `SEED))));
lutinit[31: 0] = xorshift32(xorshift32(xorshift32(xorshift32({b, a} ^ `SEED))));
end
endfunction
wire [(N+1)*8-1:0] nets;
assign nets[7:0] = din;
assign dout = nets[(N+1)*8-1:N*8];
genvar i, j;
generate
for (i = 0; i < N; i = i+1) begin:is
for (j = 0; j < 8; j = j+1) begin:js
localparam integer k = xorshift32(xorshift32(xorshift32(xorshift32((i << 20) ^ (j << 10) ^ `SEED)))) & 255;
LUT6 #(
.INIT(lutinit(i, j))
) lut (
.I0(nets[8*i+(k+0)%8]),
.I1(nets[8*i+(k+1)%8]),
.I2(nets[8*i+(k+2)%8]),
.I3(nets[8*i+(k+3)%8]),
.I4(nets[8*i+(k+4)%8]),
.I5(nets[8*i+(k+5)%8]),
.O(nets[8*i+8+j])
);
end
end
endgenerate
endmodule