add basic fuzzer for STARTUPE2

Signed-off-by: Hans Baier <hansfbaier@gmail.com>
This commit is contained in:
Hans Baier 2023-10-03 10:51:51 +07:00
parent dc7bfeba89
commit db1ae77fa2
4 changed files with 203 additions and 0 deletions

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# Copyright (C) 2017-2023 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
N := 4
include ../fuzzer.mk
database: build/segbits_cfg_center_mid.db
build/segbits_cfg_center_mid.db: $(SPECIMENS_OK)
${XRAY_SEGMATCH} -c 3 -o build/segbits_cfg_center_mid.db $$(find -name segdata_cfg_center_mid.txt)
sed -i 's/CFG_CENTER/CFG_CENTER_MID/g' $@
pushdb:
${XRAY_MERGEDB} cfg_center_mid build/segbits_cfg_center_mid.db
.PHONY: database pushdb

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
from prjxray.segmaker import Segmaker
from prjxray import segmaker
from prjxray import verilog
import os
import json
import csv
def bitfilter(frame, word):
if frame not in [26, 27]:
return False
return True
def main():
print("Loading tags")
segmk = Segmaker("design.bits")
with open('params.json', 'r') as f:
design = json.load(f)
for d in design['tiles']:
print("design: " + str(d))
site = d['site']
tile = d['tile']
connection = d['CONNECTION']
if site.startswith('STARTUP'):
segmk.add_site_tag(site, 'USRCCLKO_CONNECTED', connection == "CLOCK")
segmk.compile(bitfilter=bitfilter)
segmk.write(allow_empty=True)
if __name__ == "__main__":
main()

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# Copyright (C) 2017-2020 The Project X-Ray Authors
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
create_clock -period 10.00 [get_ports clk]
set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
write_checkpoint -force design_pre_place.dcp
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run

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#!/usr/bin/env python3
# -*- coding: utf-8 -*-
#
# Copyright (C) 2017-2020 The Project X-Ray Authors.
#
# Use of this source code is governed by a ISC-style
# license that can be found in the LICENSE file or at
# https://opensource.org/licenses/ISC
#
# SPDX-License-Identifier: ISC
import json
import io
import os
import random
random.seed(int(os.getenv("SEED"), 16))
from prjxray import util
from prjxray import lut_maker
from prjxray import verilog
from prjxray.db import Database
def gen_sites():
db = Database(util.get_db_root(), util.get_part())
grid = db.grid()
for tile_name in sorted(grid.tiles()):
if not 'CFG_CENTER_MID' in tile_name:
continue
print("// tile: " + str(tile_name))
loc = grid.loc_of_tilename(tile_name)
gridinfo = grid.gridinfo_at_loc(loc)
sites = {}
print("// " + str(gridinfo.sites.items()))
for site_name, site_type in gridinfo.sites.items():
if site_type == 'STARTUP':
print("// got site: " + str(site_name))
sites[site_type] = site_name
if sites:
yield tile_name, sites
def run():
params = {
"tiles": [],
}
for tile, sites in gen_sites():
for site_type, site in sites.items():
p = {}
p['tile'] = tile
p['site'] = site
p['CONNECTION'] = random.choice(
(
'HARD_ZERO',
# hard zero or hard one does not make a difference
# it only seems to matter if it is connected to a clock net or not
#'HARD_ONE',
'CLOCK',
))
params['tiles'].append(p)
print(
'''
module top (input wire clk);
(* KEEP, DONT_TOUCH *)
STARTUPE2 STARTUPE2 (
.CLK(1'b0),
.GSR(1'b0),
.GTS(1'b0),
.KEYCLEARB(1'b1),
.PACK(1'b0),
.PREQ(),
// Drive clock.''')
connection = p['CONNECTION']
if connection == "HARD_ZERO":
print(" .USRCCLKO (1'b0),")
elif connection == "HARD_ONE":
print(" .USRCCLKO (1'b1),")
else:
print(" .USRCCLKO (clk),")
print(
'''
.USRCCLKTS(1'b0),
.USRDONEO (1'b0),
.USRDONETS(1'b1),
.CFGCLK(),
.CFGMCLK(),
.EOS()
);
endmodule
''')
with open('params.json', 'w') as f:
json.dump(params, f, indent=2)
if __name__ == '__main__':
run()